Conflict Between Tcnt Write And Increment Operations; Conflict Between Tgr Write And Compare Match; Figure 9.48 Conflict Between Tcnt Write And Increment Operations; Figure 9.49 Conflict Between Tgr Write And Compare Match - Renesas H8SX/1520 Series Hardware Manual

9.9.5

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 9.48 shows the timing in this case.

Figure 9.48 Conflict between TCNT Write and Increment Operations

9.9.6

Conflict between TGR Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 9.49shows the timing in this case.
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Pφ
Address
Write
TCNT input
clock
TCNT
Pφ
Address
Write
Compare match
signal
TCNT
TGR

Figure 9.49 Conflict between TGR Write and Compare Match

Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT write cycle
T1 T2
TCNT
address
N M
TCNT write data
TGR write cycle
T1 T2
TGR
address
Disabled
N + 1
N
N M
TGR write data
Rev. 3.00 Mar. 14, 2006 Page 339 of 804
REJ09B0104-0300