10.10.3 Conflict Between Tcor Write And Compare-Match; 10.10.4 Conflict Between Compare-Matches A And B; Figure 10.16 Conflict Between Tcor Write And Compare-Match; Table 10.8 Timer Output Priorities - Renesas H8S/2111B Hardware Manual

10.10.3 Conflict between TCOR Write and Compare-Match

If a compare-match occurs during the T
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A,
a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC.
In this case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal
Note: * TMR_A, TMR_B

Figure 10.16 Conflict between TCOR Write and Compare-Match

10.10.4 Conflict between Compare-Matches A and B

If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
10.8.

Table 10.8 Timer Output Priorities

Output Setting
Toggle output
1 output
0 output
No change
state of a TCOR write cycle as shown in figure 10.16, the
2
TCOR write cycle by CPU
T T
1 2
TCOR address
N
N
TCOR write data
T *
3
N + 1
M
Disabled
Priority
High
Low
Rev. 1.00, 05/04, page 217 of 544