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11.9.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
TCOR write takes priority and the compare-match signal is disabled. With the TMRX, a TICR
input capture conflicts with a compare-match in the same way as with a write to TCORC. In this
case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal
Figure 11.15 Conflict between TCOR Write and Compare-Match
11.9.4
Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 11.4.
Rev. 1.00, 09/03, page 294 of 704
state of a TCOR write cycle as shown in figure 11.15, the
2
TCOR write cycle by CPU
T 1
T 2
TCOR address
N
N
N + 1
M
TCOR write data
Disabled
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