Contention Between Tcor Write And Compare Match; Contention Between Compare Matches A And B - Renesas H8S Series Hardware Manual

12.6.3

Contention between TCOR Write and Compare Match

During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a
2
compare match event occurs.
Figure 12-12 shows this operation.
ø
Address
Internal write signal
TCNT
TCOR
Compare match signal
12.6.4

Contention between Compare Matches A and B

If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the
output statuses set for compare match A and compare match B, as shown in table 12-4.
Table 12-4 Timer Output Priorities
Rev.6.00 Oct.28.2004 page 450 of 1016
REJ09B0138-0600H
Figure 12-12 Contention between TCOR Write and Compare Match
Output Setting
Toggle output
1 output
0 output
No change
TCOR write cycle by CPU
T T
1 2
TCOR address
N
N
Priority
High
Low
N+1
M
TCOR write data
Prohibited