Timer Control/Status Register (Tcsr) - Renesas H8S/2437 Hardware Manual

Renesas 16-bit single-chip microcomputer h8s family / h8s / 2600 series
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Bit
Bit Name
Initial Value
2
OCIBE
0
1
OVIE
0
0
0
10.3.7

Timer Control/Status Register (TCSR)

TCSR selects whether the counter operates or not and controls interrupt request signals.
Bit
Bit Name
Initial Value
7
ICFA
0
R/W
Description
R/W
Output Compare Interrupt B Enable
Selects whether to enable an interrupt request (OCIB)
by the OCFB flag when the OCFB flag in TCSR is set to
1.
0: OCIB requested by OCFB is disabled
1: OCIB requested by OCFB is enabled
R/W
Timer Overflow Interrupt Enable
Selects whether to enable an interrupt request (FOVI)
by the OVF flag when the OVF flag in TCSR is set to 1.
0: FOVI requested by OVF is disabled
1: FOVI requested by OVF is enabled
R
Reserved
This bit is always read as 1 and cannot be modified.
R/W
Description
R/(W)* Input Capture Flag A
This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture
signal. When BUFEA = 1, ICFA indicates that the new
FRC value has been transferred to ICRA by an input
capture signal and the old ICRA value has been moved
into ICRC.
[Setting condition]
When an input capture signal causes the FRC value to
be transferred to ICRA
[Clearing condition]
Read ICFA when ICFA = 1, then write 0 to ICFA
Rev. 1.00, 09/03, page 245 of 704

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