Timer Control/Status Register (Tcsr) - Renesas H8S Series Hardware Manual

13.2.2

Timer Control/Status Register (TCSR)

TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.
Bit Bit Name Initial Value
7 OVF 0
6 WT/IT 0
5 TME 0
4, 3 — All 1
R/W Description
R/(W) *
Overflow Flag
Indicates that TCNT has overflowed. Only a write of
0 is permitted, to clear the flag.
[Setting condition]
•
When TCNT overflows (changes from H'FF to
H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
[Clearing condition]
•
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
1: Watchdog timer mode
R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
— Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 6.00 Mar 15, 2006 page 305 of 570
Section 13 Watchdog Timer
REJ09B0211-0600