Timer Control/Status Register (Tcsr) - Renesas H8S/2100 Series Hardware Manual

13.3.5

Timer Control/Status Register (TCSR)

TCSR indicates the status flags and controls compare-match output.
• TCSR_0
Bit Bit Name
7 CMFB
6 CMFA
5 OVF
4 ADTE
3 OS3
2 OS2
Initial
Value R/W Description
0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
0 R/W A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A
1: A/D converter start requests by compare-match A
0 R/W Output Select 3 and 2
0 R/W These bits specify how the TMO0 pin output level is to
be changed by compare-match B of TCORB_0 and
TCNT_0.
00: No change
01: 0 is output
10: 1 is output
11: Output is inverted (toggle output)
are disabled
are enabled
Rev. 1.00 Apr. 28, 2008 Page 367 of 994
Section 13 8-Bit Timer (TMR)
REJ09B0452-0100