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11.1.3
Pin Configuration
Table 11-1 describes the WDT output pin.
Table 11-1 WDT Pin
Name
Watchdog timer overflow
Note: * The WDTOVF function is not available in the F-ZTAT versions.
11.1.4
Register Configuration
The WDT has three registers, as summarized in table 11-2. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 11-2 WDT Registers
Name
Timer control/status register
Timer counter
Reset control/status register
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 11.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
Symbol
I/O
WDTOVF * Output
Abbreviation
R/W
R/(W) *
TCSR
TCNT
R/W
R/(W) *
RSTCSR
Function
Outputs counter overflow signal in watchdog
timer mode
Initial Value
3
H'18
H'00
3
H'1F
Rev. 5.00, 12/03, page 409 of 1088
1
Address *
2
Write *
Read
H'FFBC
H'FFBC
H'FFBC
H'FFBD
H'FFBE
H'FFBF
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