11.2.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
Bit Name
Initial Value
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit
Bit Name
7
OVF
6
WT/IT
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7
6
OVF
WT/IT
0
0
R/(W)*
R/W
Initial
Value
R/W
0
R/(W)* Overflow Flag
0
R/W
5
4
TME
—
0
1
R/W
R
Description
Indicates that TCNT has overflowed in interval timer
mode. Only 0 can be written to this bit, to clear the flag.
[Setting condition]
•
When TCNT overflows in interval timer mode
(changes from H'FF to H'00)
•
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
[Clearing condition]
•
Cleared by reading TCSR when OVF = 1, then writing
0 to OVF
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows while RSTE = 1, this LSI is
initialized initially.
Section 11 Watchdog Timer (WDT)
3
2
1
—
CKS2
CKS1
1
0
0
R
R/W
R/W
Rev. 3.00 Mar. 14, 2006 Page 369 of 804
0
CKS0
0
R/W
REJ09B0104-0300