Timer Control/Status Register (Tcsr) - Renesas H8SX/1650 Hardware Manual

TCR
Bit 2 Bit 1
Channel CKS2 CKS1
All 1 0
1 1
1 1
Notes: 1. If the clock input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. To use the external clock, the DDR and ICR bits in the corresponding pin should be set
to 0 and 1, respectively. For details, see section 8, I/O Ports.
11.3.6

Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.
TCSR_0
7
Bit
CMFB
Bit Name
Initial Value 0
R/W R/(W)*
TCSR_1
7
Bit
CMFB
Bit Name
0
Initial Value
R/(W)*
R/W
Note: * Only 0 can be written to this bit, to clear the flag.
TCCR
Bit 0 Bit 1 Bit 0
CKS0 ICKS1 ICKS0
 
1
 
0
 
1
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
6 5
CMFA OVF
0 0
R/(W)* R/(W)*
Description
Uses external clock. Counts at rising edge*
Uses external clock. Counts at falling edge*
Uses external clock. Counts at both rising and falling
2
edges* .
4 3
ADTE OS3
0 0
R/W R/W
4 3
OS3
1 0
R R/W
Rev.2.00 Jun. 28, 2007 Page 421 of 666
Section 11 8-Bit Timers (TMR)
2
.
2
.
2 1
OS2 OS1
0 0
R/W R/W
2 1
OS2 OS1
0 0
R/W R/W
REJ09B0311-0200
0
OS0
0
R/W
0
OS0
0
R/W