Sign In
Upload
Manuals
Brands
Renesas Manuals
Computer Hardware
F-ZTAT H8 Series
Renesas F-ZTAT H8 Series Manuals
Manuals and User Guides for Renesas F-ZTAT H8 Series. We have
3
Renesas F-ZTAT H8 Series manuals available for free PDF download: Hardware Manual
Renesas F-ZTAT H8 Series Hardware Manual (905 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 8.58 MB
Table of Contents
Sample Program
7
Table of Contents
11
Section 1 Overview
25
Overview
25
Block Diagram
31
Pin Description
32
Pin Arrangement
32
Pin Assignments in each Mode
34
Pin Functions
39
Differences between H8/3048F and H8/3048F-ONE
44
Section 2 CPU
49
Overview
49
Features
49
Differences from H8/300 CPU
50
CPU Operating Modes
51
Address Space
52
Register Configuration
53
Overview
53
General Registers
54
Control Registers
55
Initial CPU Register Values
56
Data Formats
57
General Register Data Formats
57
Memory Data Formats
59
Instruction Set
60
Instruction Set Overview
60
Instructions and Addressing Modes
61
Tables of Instructions Classified by Function
62
Basic Instruction Formats
71
Notes on Use of Bit Manipulation Instructions
72
Addressing Modes and Effective Address Calculation
74
Addressing Modes
74
Effective Address Calculation
76
Processing States
80
Overview
80
Program Execution State
81
Exception-Handling State
81
Exception-Handling Sequences
83
Bus-Released State
84
Reset State
84
Power-Down State
84
Basic Operational Timing
85
Overview
85
On-Chip Memory Access Timing
85
On-Chip Supporting Module Access Timing
86
Access to External Address Space
87
Section 3 MCU Operating Modes
89
Overview
89
Operating Mode Selection
89
Register Configuration
90
Mode Control Register (MDCR)
90
System Control Register (SYSCR)
91
Operating Mode Descriptions
93
Mode 1
93
Mode 2
93
Mode 3
93
Mode 4
93
Mode 5
93
Mode 6
94
Mode 7
94
Pin Functions in each Operating Mode
94
Memory Map in each Operating Mode
95
Section 4 Exception Handling
105
Overview
105
Exception Handling Types and Priority
105
Exception Handling Operation
105
Exception Vector Table
106
Reset
108
Overview
108
Reset Sequence
108
Interrupts after Reset
111
Interrupts
112
Trap Instruction
113
Stack Status after Exception Handling
113
Notes on Stack Usage
114
Section 5 Interrupt Controller
115
Overview
115
Features
115
Block Diagram
116
Pin Configuration
117
Register Configuration
117
Register Descriptions
118
System Control Register (SYSCR)
118
Interrupt Priority Registers a and B (IPRA, IPRB)
119
IRQ Status Register (ISR)
126
IRQ Enable Register (IER)
127
IRQ Sense Control Register (ISCR)
128
Interrupt Sources
129
External Interrupts
129
Internal Interrupts
130
Interrupt Vector Table
130
Interrupt Operation
134
Interrupt Handling Process
134
Interrupt Sequence
139
Interrupt Response Time
140
Usage Notes
141
Contention between Interrupt and Interrupt-Disabling Instruction
141
Instructions that Inhibit Interrupts
142
Interrupts During EEPMOV Instruction Execution
142
Usage Notes on External Interrupts
142
Notes on Non-Maskable Interrupts (NMI)
144
Section 6 Bus Controller
147
Overview
147
Features
147
Block Diagram
148
Input/Output Pins
149
Register Configuration
150
Register Descriptions
150
Bus Width Control Register (ABWCR)
150
Access State Control Register (ASTCR)
151
Wait Control Register (WCR)
152
Wait State Controller Enable Register (WCER)
153
Bus Release Control Register (BRCR)
154
Chip Select Control Register (CSCR)
155
Operation
157
Area Division
157
Chip Select Signals
158
Data Bus
160
Bus Control Signal Timing
161
Wait Modes
169
Interconnections with Memory (Example)
175
Bus Arbiter Operation
177
Usage Notes
180
Connection to Dynamic RAM and Pseudo-Static RAM
180
Register Write Timing
180
BREQ Input Timing
182
Transition to Software Standby Mode
182
Section 7 Refresh Controller
183
Overview
183
Features
183
Block Diagram
184
Input/Output Pins
185
Register Configuration
185
Register Descriptions
186
Refresh Control Register (RFSHCR)
186
Refresh Timer Control/Status Register (RTMCSR)
189
Refresh Timer Counter (RTCNT)
190
Refresh Time Constant Register (RTCOR)
191
Operation
192
Overview
192
DRAM Refresh Control
194
Pseudo-Static RAM Refresh Control
209
Interval Timer
213
Interrupt Source
219
Usage Notes
219
Section 8 DMA Controller
221
Overview
221
Features
221
Block Diagram
222
Functional Overview
223
Input/Output Pins
225
Register Configuration
225
Register Descriptions (Short Address Mode)
227
Memory Address Registers (MAR)
227
I/O Address Registers (IOAR)
228
Execute Transfer Count Registers (ETCR)
229
Data Transfer Control Registers (DTCR)
230
Register Descriptions (Full Address Mode)
233
Memory Address Registers (MAR)
233
I/O Address Registers (IOAR)
233
Execute Transfer Count Registers (ETCR)
234
Data Transfer Control Registers (DTCR)
236
Operation
242
Overview
242
I/O Mode
244
Idle Mode
246
Repeat Mode
249
Normal Mode
253
Block Transfer Mode
256
DMAC Activation
261
DMAC Bus Cycle
263
DMAC Multiple-Channel Operation
269
External Bus Requests, Refresh Controller, and DMAC
270
NMI Interrupts and DMAC
271
Aborting a DMA Transfer
272
Exiting Full Address Mode
273
DMAC States in Reset State, Standby Modes, and Sleep Mode
274
Interrupts
275
Usage Notes
276
Note on Word Data Transfer
276
DMAC Self-Access
276
Longword Access to Memory Address Registers
276
Note on Full Address Mode Setup
276
Note on Activating DMAC by Internal Interrupts
276
NMI Interrupts and Block Transfer Mode
278
Memory and I/O Address Register Values
278
Bus Cycle When Transfer Is Aborted
279
Section 9 I/O Ports
281
Overview
281
Port 1
285
Overview
285
Register Descriptions
286
Port 2
288
Overview
288
Register Descriptions
289
Port 3
292
Overview
292
Register Descriptions
292
Port 4
294
Overview
294
Register Descriptions
295
Port 5
298
Overview
298
Register Descriptions
299
Port 6
302
Overview
302
Register Descriptions
303
Port 7
306
Overview
306
Register Description
307
Port 8
308
Overview
308
Register Descriptions
309
Port 9
313
Overview
313
Register Descriptions
314
Port a
318
Overview
318
Register Descriptions
320
Pin Functions
322
Port B
330
Overview
330
Register Descriptions
332
Pin Functions
334
Section 10 16-Bit Integrated Timer Unit (ITU)
339
Overview
339
Features
339
Block Diagrams
342
Input/Output Pins
347
Register Configuration
348
Register Descriptions
351
Timer Start Register (TSTR)
351
Timer Synchro Register (TSNC)
352
Timer Mode Register (TMDR)
354
Timer Function Control Register (TFCR)
357
Timer Output Master Enable Register (TOER)
359
Timer Output Control Register (TOCR)
361
Timer Counters (TCNT)
362
General Registers (GRA, GRB)
363
Buffer Registers (BRA, BRB)
364
Timer Control Registers (TCR)
365
Timer I/O Control Register (TIOR)
367
Timer Status Register (TSR)
369
Timer Interrupt Enable Register (TIER)
371
CPU Interface
373
16-Bit Accessible Registers
373
8-Bit Accessible Registers
375
Operation
376
Overview
376
Basic Functions
377
Synchronization
386
PWM Mode
388
Reset-Synchronized PWM Mode
392
Complementary PWM Mode
395
Phase Counting Mode
404
Buffering
406
ITU Output Timing
413
Interrupts
415
Setting of Status Flags
415
Clearing of Status Flags
417
Interrupt Sources and DMA Controller Activation
418
Usage Notes
419
Section 11 Programmable Timing Pattern Controller
435
Overview
435
Features
435
Block Diagram
436
TPC Pins
437
Registers
438
Register Descriptions
439
Port a Data Direction Register (PADDR)
439
Port a Data Register (PADR)
439
Port B Data Direction Register (PBDDR)
440
Port B Data Register (PBDR)
440
Next Data Register a (NDRA)
441
Next Data Register B (NDRB)
443
Next Data Enable Register a (NDERA)
445
Next Data Enable Register B (NDERB)
446
TPC Output Control Register (TPCR)
447
TPC Output Mode Register (TPMR)
449
Operation
451
Overview
451
Output Timing
452
Normal TPC Output
453
Non-Overlapping TPC Output
455
TPC Output Triggering by Input Capture
457
Usage Notes
458
Operation of TPC Output Pins
458
Note on Non-Overlapping Output
458
Section 12 Watchdog Timer
461
Overview
461
Features
461
Block Diagram
462
Pin Configuration
462
Register Configuration
463
Register Descriptions
463
Timer Counter (TCNT)
463
Timer Control/Status Register (TCSR)
464
Reset Control/Status Register (RSTCSR)
466
Notes on Register Access
467
Operation
469
Watchdog Timer Operation
469
Interval Timer Operation
470
Timing of Setting of Overflow Flag (OVF)
470
Timing of Setting of Watchdog Timer Reset Bit (WRST)
471
Interrupts
472
Usage Notes
472
Notes
473
Section 13 Serial Communication Interface
475
Overview
475
Features
475
Block Diagram
477
Input/Output Pins
478
Register Configuration
478
Register Descriptions
479
Receive Shift Register (RSR)
479
Receive Data Register (RDR)
479
Transmit Shift Register (TSR)
480
Transmit Data Register (TDR)
480
Serial Mode Register (SMR)
481
Serial Control Register (SCR)
484
Serial Status Register (SSR)
488
Bit Rate Register (BRR)
492
Operation
500
Overview
500
Operation
504
Operation in Asynchronous Mode
506
Multiprocessor Communication
515
Synchronous Operation
522
SCI Interrupts
526
Usage Notes
531
Section 14 Smart Card Interface
533
Overview
533
Features
533
Block Diagram
534
Input/Output Pins
535
Register Configuration
535
Register Descriptions
536
Smart Card Mode Register (SCMR)
536
Advertisement
Renesas F-ZTAT H8 Series Hardware Manual (845 pages)
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.52 MB
Table of Contents
Table of Contents
15
Section 1 Overview
29
Overview
29
Block Diagram
34
Pin Description
35
Pin Arrangement
35
Pin Assignments in each Mode
36
Pin Functions
41
Section 2 CPU
47
Overview
47
Features
47
Differences from H8/300 CPU
48
CPU Operating Modes
49
Address Space
50
Register Configuration
51
Overview
51
General Registers
52
Control Registers
53
Initial CPU Register Values
54
Data Formats
55
General Register Data Formats
55
Memory Data Formats
57
Instruction Set
58
Instruction Set Overview
58
Instructions and Addressing Modes
59
Tables of Instructions Classified by Function
60
Basic Instruction Formats
70
Notes on Use of Bit Manipulation Instructions
71
Addressing Modes and Effective Address Calculation
72
Addressing Modes
72
Effective Address Calculation
75
Processing States
79
Overview
79
Program Execution State
80
Exception-Handling State
80
Exception-Handling Sequences
82
Bus-Released State
83
Reset State
83
Power-Down State
83
Basic Operational Timing
84
Overview
84
On-Chip Memory Access Timing
84
On-Chip Supporting Module Access Timing
85
Access to External Address Space
86
Section 3 MCU Operating Modes
87
Overview
87
Operating Mode Selection
87
Register Configuration
88
Mode Control Register (MDCR)
88
System Control Register (SYSCR)
89
Operating Mode Descriptions
91
Mode 1
91
Mode 2
91
Mode 3
91
Mode 4
91
Mode 5
91
Mode 6
92
Mode 7
92
Pin Functions in each Operating Mode
92
Memory Map in each Operating Mode
93
Section 4 Exception Handling
97
Overview
97
Exception Handling Types and Priority
97
Exception Handling Operation
97
Exception Sources and Vector Table
98
Reset
100
Overview
100
Reset Sequence
100
Interrupts after Reset
103
Interrupts
104
Trap Instruction
105
Stack Status after Exception Handling
105
Notes on Use of the Stack
106
Section 5 Interrupt Controller
107
Overview
107
Features
107
Block Diagram
108
Pin Configuration
109
Register Configuration
109
Register Descriptions
110
System Control Register (SYSCR)
110
Interrupt Priority Registers a and B (IPRA, IPRB)
111
IRQ Status Register (ISR)
117
IRQ Enable Register (IER)
118
IRQ Sense Control Register (ISCR)
119
Interrupt Sources
120
External Interrupts
120
Internal Interrupts
121
Interrupt Exception Vector Table
121
Interrupt Operation
125
Interrupt Handling Process
125
Interrupt Exception Handling Sequence
130
Interrupt Response Time
131
Usage Notes
132
Contention between Interrupt Generation and Disabling
132
Instructions that Inhibit Interrupts
133
Interrupts During EEPMOV Instruction Execution
133
Notes on Use of External Interrupts
133
Section 6 Bus Controller
137
Overview
137
Features
137
Block Diagram
138
Pin Configuration
139
Register Configuration
140
Register Descriptions
140
Bus Width Control Register (ABWCR)
140
Access State Control Register (ASTCR)
141
Wait Control Register (WCR)
142
Wait State Controller Enable Register (WCER)
143
Bus Release Control Register (BRCR)
144
Chip Select Control Register (CSCR)
146
Operation
147
Area Division
147
Chip Select Signals
149
Data Bus
150
Bus Control Signal Timing
151
Wait Modes
159
Interconnections with Memory (Example)
165
Bus Arbiter Operation
167
Usage Notes
170
Connection to Dynamic RAM and Pseudo-Static RAM
170
Register Write Timing
170
BREQ Input Timing
172
Transition to Software Standby Mode
172
Section 7 Refresh Controller
173
Overview
173
Features
173
Block Diagram
175
Pin Configuration
176
Register Configuration
176
Register Descriptions
177
Refresh Control Register (RFSHCR)
177
Refresh Timer Control/Status Register (RTMCSR)
180
Refresh Timer Counter (RTCNT)
181
Refresh Time Constant Register (RTCOR)
182
Operation
183
Overview
183
DRAM Refresh Control
185
Pseudo-Static RAM Refresh Control
200
Interval Timer
204
Interrupt Source
210
Usage Notes
210
Section 8 DMA Controller
213
Overview
213
Features
213
Block Diagram
214
Functional Overview
215
Pin Configuration
217
Register Configuration
217
Register Descriptions (Short Address Mode)
219
Memory Address Registers (MAR)
220
I/O Address Registers (IOAR)
221
Execute Transfer Count Registers (ETCR)
222
Data Transfer Control Registers (DTCR)
223
Register Descriptions (Full Address Mode)
226
Memory Address Registers (MAR)
226
I/O Address Registers (IOAR)
227
Execute Transfer Count Registers (ETCR)
227
Data Transfer Control Registers (DTCR)
229
Operation
234
Overview
234
I/O Mode
236
Idle Mode
238
Repeat Mode
241
Normal Mode
245
Block Transfer Mode
248
DMAC Activation
253
DMAC Bus Cycle
255
DMAC Multiple-Channel Operation
261
External Bus Requests, Refresh Controller, and DMAC
262
NMI Interrupts and DMAC
263
Aborting a DMA Transfer
264
Exiting Full Address Mode
265
DMAC States in Reset State, Standby Modes, and Sleep Mode
266
Interrupts
267
Usage Notes
268
Note on Word Data Transfer
268
DMAC Self-Access
268
Longword Access to Memory Address Registers
268
Note on Full Address Mode Setup
268
Note on Activating DMAC by Internal Interrupts
268
NMI Interrupts and Block Transfer Mode
270
Memory and I/O Address Register Values
270
Bus Cycle When Transfer Is Aborted
271
Section 9 I/O Ports
273
Overview
273
Port 1
277
Overview
277
Overview
280
Register Configuration
281
Port 3
284
Overview
284
Port 4
286
Overview
286
Port 5
290
Overview
290
Port 6
294
Overview
294
Register Configuration
295
Port 7
298
Overview
298
Register Configuration
299
Port 8
300
Overview
300
Register Configuration
301
Port 9
305
Overview
305
Register Configuration
306
Port a
309
Overview
309
Register Configuration
311
Pin Functions
313
Port B
321
Overview
321
Register Configuration
323
Pin Functions
325
Section 10 16-Bit Integrated Timer Unit (ITU)
331
Overview
331
Features
331
Block Diagrams
334
Pin Configuration
339
Register Configuration
340
Register Descriptions
343
Timer Start Register (TSTR)
343
Timer Synchro Register (TSNC)
344
Timer Mode Register (TMDR)
346
Timer Function Control Register (TFCR)
349
Timer Output Master Enable Register (TOER)
351
Timer Output Control Register (TOCR)
353
Timer Counters (TCNT)
354
General Registers (GRA, GRB)
355
Buffer Registers (BRA, BRB)
356
Timer Control Registers (TCR)
357
Timer I/O Control Register (TIOR)
359
Timer Status Register (TSR)
361
Timer Interrupt Enable Register (TIER)
363
CPU Interface
365
16-Bit Accessible Registers
365
8-Bit Accessible Registers
367
Operation
368
Overview
368
Basic Functions
369
Synchronization
378
PWM Mode
379
Reset-Synchronized PWM Mode
383
Complementary PWM Mode
386
Phase Counting Mode
395
Buffering
397
ITU Output Timing
404
Interrupts
406
Setting of Status Flags
406
Clearing of Status Flags
408
Interrupt Sources and DMA Controller Activation
409
Usage Notes
410
Section 11 Programmable Timing Pattern Controller
425
Overview
425
Features
425
Block Diagram
426
Pin Configuration
427
Register Configuration
428
Register Descriptions
429
Port a Data Direction Register (PADDR)
429
Port a Data Register (PADR)
429
Port B Data Direction Register (PBDDR)
430
Port B Data Register (PBDR)
430
Next Data Register a (NDRA)
431
Next Data Register B (NDRB)
433
Next Data Enable Register a (NDERA)
435
Next Data Enable Register B (NDERB)
436
TPC Output Control Register (TPCR)
437
TPC Output Mode Register (TPMR)
439
Operation
441
Overview
441
Output Timing
442
Normal TPC Output
443
Non-Overlapping TPC Output
445
TPC Output Triggering by Input Capture
447
Usage Notes
448
Operation of TPC Output Pins
448
Note on Non-Overlapping Output
448
Section 12 Watchdog Timer
451
Overview
451
Features
451
Block Diagram
452
Register Configuration
452
Register Descriptions
453
Timer Counter (TCNT)
453
Timer Control/Status Register (TCSR)
454
Reset Control/Status Register (RSTCSR)
456
Notes on Register Access
457
Operation
458
Watchdog Timer Operation
458
Interval Timer Operation
459
Timing of Setting of Overflow Flag (OVF)
460
Timing of Setting of Watchdog Timer Reset Bit (WRST)
461
Interrupts
462
Usage Notes
462
Section 13 Serial Communication Interface
463
Overview
463
Features
463
Block Diagram
465
Pin Configuration
466
Register Configuration
466
Register Descriptions
467
Receive Shift Register (RSR)
467
Receive Data Register (RDR)
467
Transmit Shift Register (TSR)
468
Transmit Data Register (TDR)
468
Serial Mode Register (SMR)
469
Serial Control Register (SCR)
472
Serial Status Register (SSR)
476
Bit Rate Register (BRR)
480
Operation
490
Overview
490
Operation in Asynchronous Mode
492
Multiprocessor Communication
501
Synchronous Operation
508
SCI Interrupts
516
Usage Notes
517
Renesas F-ZTAT H8 Series Hardware Manual (562 pages)
8-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 3.29 MB
Table of Contents
Table of Contents
17
Section 1 Overview
27
Overview
27
Internal Block Diagram
32
Pin Arrangement and Functions
34
Pin Arrangement
34
Pin Functions
46
Section 2 CPU
53
Overview
53
Features
53
Address Space
54
Register Configuration
54
Register Descriptions
55
General Registers
55
Control Registers
55
Initial Register Values
57
Data Formats
57
Data Formats in General Registers
58
Memory Data Formats
59
Addressing Modes
60
Effective Address Calculation
62
Instruction Set
66
Data Transfer Instructions
68
Arithmetic Operations
70
Logic Operations
71
Shift Operations
71
Bit Manipulations
73
Branching Instructions
77
System Control Instructions
79
Block Data Transfer Instruction
80
Basic Operational Timing
81
Access to On-Chip Memory (RAM, ROM)
81
Access to On-Chip Peripheral Modules
82
CPU States
83
Overview
83
Program Execution State
85
Program Halt State
85
Exception-Handling State
85
Memory Map
86
Application Notes
88
Notes on Data Access
88
Notes on Bit Manipulation
90
Notes on Use of the EEPMOV Instruction
96
Section 3 Exception Handling
97
Overview
97
Reset
97
Reset Sequence
97
Interrupt Immediately after Reset
98
Interrupts
99
Overview
99
Interrupt Control Registers
101
External Interrupts
109
Internal Interrupts
110
Interrupt Operations
110
Interrupt Response Time
115
Application Notes
115
Notes on Stack Area Use
115
Notes on Rewriting Port Mode Registers
116
Section 4 Clock Pulse Generators
119
Overview
119
Block Diagram
119
System Clock and Subclock
119
System Clock Generator
120
Subclock Generator
122
Prescalers
125
Note on Oscillators
126
Section 5 Power-Down Modes
127
Overview
127
System Control Registers
130
Sleep Mode
133
Transition to Sleep Mode
133
Clearing Sleep Mode
133
Standby Mode
134
Transition to Standby Mode
134
Clearing Standby Mode
134
Oscillator Settling Time after Standby Mode Is Cleared
134
Transition to Standby Mode and Port Pin States
135
Notes on External Input Signal Changes Before/After Standby Mode
136
Watch Mode
137
Transition to Watch Mode
137
Clearing Watch Mode
138
Oscillator Settling Time after Watch Mode Is Cleared
138
Notes on External Input Signal Changes Before/After Watch Mode
138
Subsleep Mode
138
Transition to Subsleep Mode
138
Clearing Subsleep Mode
139
Subactive Mode
139
Transition to Subactive Mode
139
Clearing Subactive Mode
139
Operating Frequency in Subactive Mode
140
Active (Medium-Speed) Mode
140
Transition to Active (Medium-Speed) Mode
140
Clearing Active (Medium-Speed) Mode
140
Operating Frequency in Active (Medium-Speed) Mode
140
Direct Transfer
141
Direct Transfer Overview
141
Calculation of Direct Transfer Time before Transition
142
Notes on External Input Signal Changes Before/After Direct Transition
144
Section 6 ROM
145
Overview
145
Block Diagram
145
Overview of Flash Memory
146
Features
146
Block Diagram
147
Flash Memory Operating Modes
148
Pin Configuration
151
Register Configuration
152
Flash Memory Register Descriptions
152
Flash Memory Control Register 1 (FLMCR1)
152
Flash Memory Control Register 2 (FLMCR2)
155
Erase Block Register (EBR)
156
Mode Control Register (MDCR)
157
System Control Register 3 (SYSCR3)
157
On-Board Programming Modes
158
Boot Mode
159
User Program Mode
164
Flash Memory Programming/Erasing
166
Program Mode
166
Program-Verify Mode
167
Erase Mode
169
Erase-Verify Mode
169
Flash Memory Protection
171
Hardware Protection
171
Software Protection
172
Error Protection
172
Interrupt Handling During Flash Memory Programming and Erasing
174
Flash Memory Writer Mode
175
Writer Mode Setting
175
Socket Adapter and Memory Map
175
Writer Mode Operation
179
Memory Read Mode
180
Auto-Program Mode
184
Auto-Erase Mode
186
Status Read Mode
187
Status Polling
188
Writer Mode Transition Time
189
Notes on Memory Programming
189
Flash Memory Programming and Erasing Precautions
190
Notes When Converting the F-ZTAT Application Software to the Mask-ROM Versions
192
Section 7 RAM
193
Overview
193
Block Diagram
193
Section 8 I/O Ports
195
Overview
195
Port 1
198
Overview
198
Register Configuration and Description
199
Pin Functions
204
Pin States
207
MOS Input Pull-Up
208
Port 2
208
Overview
208
Register Configuration and Description
209
Pin Functions
213
Pin States
214
Port 3 (H8/3857 Group Only)
215
Overview
215
Register Configuration and Description
215
Pin Functions
218
Pin States
219
MOS Input Pull-Up
219
Port 4
220
Overview
220
Register Configuration and Description
220
Pin Functions
222
Pin States
223
Port 5
223
Overview
223
Register Configuration and Description
224
Pin Functions
226
Pin States
226
MOS Input Pull-Up
226
Port 9 [Chip-Internal I/O Port]
227
Overview
227
Register Configuration and Description
227
Pin Functions
228
Pin States
229
Port a [Chip-Internal I/O Port]
229
Overview
229
Register Configuration and Description
230
Pin Functions
231
Pin States
231
Port B
232
Overview
232
Register Configuration and Description
233
Section 9 Timers
235
Overview
235
Timer a
236
Overview
236
Register Descriptions
238
Timer Operation
240
Timer a Operation States
241
Timer B
241
Overview
241
Register Descriptions
243
Timer Operation
245
Timer B Operation States
246
Timer C (H8/3857 Group Only)
246
Overview
246
Register Descriptions
248
Timer Operation
250
Timer C Operation States
252
Timer F
252
Overview
252
Register Descriptions
255
Interface with the CPU
261
Timer Operation
264
Application Notes
266
Watchdog Timer [H8/3857F and H8/3854F Only]
267
Overview
267
Register Descriptions
269
Operation
272
Watchdog Timer Operating Modes
273
Section 10 Serial Communication Interface
275
Overview
275
SCI1 (H8/3857 Group Only)
276
Overview
276
Register Descriptions
278
Operation
282
Interrupts
285
Application Notes
285
Sci3
286
Overview
286
Register Descriptions
288
Operation
305
Operation in Asynchronous Mode
309
Operation in Synchronous Mode
318
Multiprocessor Communication Function
325
Interrupts
331
Application Notes
332
Section 11 14-Bit PWM (H8/3857 Group Only)
337
Overview
337
Features
337
Block Diagram
337
Pin Configuration
338
Register Configuration
338
Register Descriptions
338
PWM Control Register (PWCR)
338
PWM Data Registers U and L (PWDRU, PWDRL)
339
Operation
340
Advertisement
Advertisement
Related Products
Renesas F-ZTAT Super H Series
Renesas F-ZTAT H8/3854
Renesas F-ZTAT Series
Renesas FP-100B
Renesas FP-144
Renesas FP-144L
Renesas FP-80Q
Renesas SH7206 FP-176C
Renesas FreeRTOS DA16200
Renesas FSL-T06
Renesas Categories
Computer Hardware
Motherboard
Microcontrollers
Adapter
Switch
More Renesas Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL