Timer Control/Status Register (Tcsr) - Renesas H8SX/1500 Series Hardware Manual

11.2.2

Timer Control/Status Register (TCSR)

TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit 7
Bit Name OVF
Initial Value 0
R/W R/(W)*
Note: * Only 0 can be written to this bit, to clear the flag.
Bit Bit Name
7 OVF
6 WT/IT
6 5
WT/IT TME
0 0
R/W R/W
Initial
Value R/W Description
0 R/(W)* Overflow Flag
Indicates that TCNT has overflowed in interval timer
mode. Only 0 can be written to this bit, to clear the flag.
[Setting condition]
•
•
[Clearing condition]
•
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
4 3
— —
1 1
R R
When TCNT overflows in interval timer mode
(changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
Cleared by reading TCSR when OVF = 1, then writing
0 to OVF
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
When TCNT overflows while RSTE = 1, this LSI is
initialized initially.
Rev. 3.00 Mar. 14, 2006 Page 369 of 804
Section 11 Watchdog Timer (WDT)
2 1
CKS2 CKS1
0 0
R/W R/W
REJ09B0104-0300
0
CKS0
0
R/W