Register Descriptions; Timer Counter (Tcnt); Timer Control/Status Register (Tcsr) - Renesas H8S Series Hardware Manual

13.2

Register Descriptions

13.2.1

Timer Counter (TCNT)

Bit : 7
Initial value : 0
R/W : R/W
TCNT is an 8-bit readable/writable*
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by
bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow
2
signal (WDTOVF)* or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit
in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized
in software standby mode.
Notes: 1. TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4,
Notes on Register Access.
2. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or
H8S/2390.
13.2.2

Timer Control/Status Register (TCSR)

Bit : 7
OVF
Initial value : 0
R/W : R/(W)*
Note: * Can only be written with 0 for flag clearing.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the
timer mode.
TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on
Register Access.
Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This
flag cannot be set during watchdog timer operation.
Bit 7
OVF Description
0 [Clearing condition]
Cleared by reading TCSR when OVF = 1, then writing 0 to OVF
1 [Setting condition]
Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode
Rev.6.00 Oct.28.2004 page 456 of 1016
REJ09B0138-0600H
6 5 4
0 0 0
R/W R/W R/W
1
up-counter.
6 5 4
WT/IT TME —
0 0 1
R/W R/W —
3 2 1
0 0 0
R/W R/W R/W
3 2 1
— CKS2 CKS1
1 0 0
— R/W R/W
0
0
R/W
0
CKS0
0
R/W
(Initial value)