Table of Contents
Advertisement
Section 4 Resets
4.3.3
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT of the watchdog timer, and the timer mode.
• TCSR_0
Initial
Bit
Bit Name
Value
7
OVF
0
6
WT/IT
0
5
TME
0
4
0
3
RST/NMI
0
Rev. 1.00 May 09, 2008 Page 80 of 954
REJ09B0462-0100
R/W
Description
R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF to
H'00).
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by the
internal reset.
[Clearing conditions]
•
When TCSR is read when OVF = 1, then 0 is written to
OVF
•
When 0 is written to TME
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
R/W
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
Reserved
R/W
The initial value should not be changed.
Reset or NMI
R/W
Selects to request an internal reset or an NMI interrupt when
TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
Advertisement
Table of Contents
