Timer Control/Status Register (Tcsr); Table 12.2 Clock Input To Tcnt And Count Condition - Renesas H8S/2368 Series Hardware Manual

Table 12.2 Clock Input to TCNT and Count Condition

Channel Bit 2
CKS2
TMR_0 0
1
TMR_1 0
1
All 1
Note: * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting.
12.3.5

Timer Control/Status Register (TCSR)

TCSR displays status flags, and controls compare match output.
TCSR_0
Bit Bit Name
7 CMFB
Rev. 2.00, 05/03, page 478 of 820
TCR
Bit 1 Bit 0
CKS1 CKS0
0 0
1
1 0
1
0 0
0 0
1
1 0
1
0 0
0 1
1 0
1 1
Initial Value R/W
0 R/(W)*
Description
Clock input disabled
Internal clock, counted at falling edge of φ/8
Internal clock, counted at falling edge of φ/64
Internal clock, counted at falling edge of φ/8192
Count at TCNT_1 overflow signal*
Clock input disabled
Internal clock, counted at falling edge of φ/8
Internal clock, counted at falling edge of φ/64
Internal clock, counted at falling edge of φ/8192
Count at TCNT_0 compare match A*
External clock, counted at rising edge
External clock, counted at falling edge
External clock, counted at both rising and falling edges
Description
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0