Table of Contents
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Contents
Addressing Circular Buffers ................................................... 5-12
Addressing With Bit-reversed Addresses ................................. 5-15
Modifying DAG and Pointer Registers ........................................ 5-15
Memory Address Alignment ........................................................ 5-16
AAU Instruction Summary ......................................................... 5-19
Memory Architecture .................................................................... 6-2
Overview of On-Chip Level 1 (L1) Memory ............................ 6-2
Overview of Scratchpad Data SRAM ....................................... 6-4
Overview of On-Chip Level 2 (L2) Memory ............................ 6-4
L1 Instruction Memory ................................................................ 6-5
IMEM_CONTROL Register .................................................. 6-5
L1 Instruction SRAM ............................................................. 6-7
L1 Instruction Cache ............................................................ 6-10
Cache Lines ...................................................................... 6-10
Cache Hits and Misses .................................................. 6-13
Cache Line Fills ............................................................ 6-14
Line Fill Buffer ............................................................. 6-15
Cache Line Replacement ............................................... 6-15
Instruction Cache Management ........................................ 6-16
Instruction Cache Locking by Line ................................ 6-16
Instruction Cache Locking by Way ................................ 6-17
Instruction Cache Invalidation ...................................... 6-18
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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Table of Contents
