Interrupt Latency - Analog Devices ADSP-2106x SHARC User Manual

3 Program Sequencing
At the end of the interrupt service routine, the RTI instruction causes
the following actions:
1. Returns to the address stored at the top of the PC stack.
2. Pops this value off of the PC stack.
3. Pops the status stack if the ASTAT and MODE1 status registers were
pushed (for the
vector interrupt).
4. Clears the appropriate bit in the interrupt latch register (IRPTL) and
interrupt mask pointer (IMASKP).
All interrupt service routines, except for reset, should end with a
return-from-interrupt (RTI) instruction. After reset, the PC stack is
empty, so there is no return address—the last instruction of the reset
service routine should be a jump to the start of your program.
3.6.1

Interrupt Latency

The ADSP-2106x responds to interrupts in three stages:
synchronization and latching (1 cycle), recognition (1 cycle), and
branching to the interrupt vector (2 cycles). See Figure 3.10. If an
interrupt is forced in software by a write to a bit in IRPTL, it is
recognized in the following cycle, and the two cycles of branching to
the interrupt vector follow that.
For most interrupts, internal and external, only one instruction is
executed after the interrupt occurs (and before the two instructions
aborted) while the processor fetches and decodes the first instruction
of the service routine. Because of the one-cycle delay between an
arithmetic exception and the STKY register update, however, there are
two cycles after an arithmetic exception occurs before interrupt
processing starts.
The standard latency associated with the
multiprocessor vector interrupt are:
Interrupt
IRQ
interrupts
2-0
Multiprocessor vector interrupt (VIRPT register)
3 – 22
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IRQ
external interrupts, timer interrupt, or VIRPT
2-0
IRQ
interrupts and the
2-0
Latency (minimum)
3 cycles
6 cycles