Interrupt Latency - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

Table of Contents

The following situations also incur additional stall cycles.

1. Attempting to write to (or read from) a full (or empty) DMA

buffer (IDP and SPORT) causes the core to hang indefinitely,

2. In case of a full write data FIFO, the held-offI/O processor register

read or write access incurs one extra core-clock cycle.

3. Interrupted IOP register reads and writes, if preceded by another

write creates one additional core stall cycle.

Interrupt Latency

During an interrupt-driven I/O transfer from any peripheral that uses an

IOP interrupt service routine, a write into an IOP register to clear the

interrupt causes a certain amount of latency. If the program comes out of

the interrupt service routine during that period of latency, the interrupt is

generated again.

To avoid the interrupt from being regenerated, use one of the following

1. Read an IOP register from the same peripheral block before the

return from interrupt (

shown in the example code below.

ISR_Routine:

dm(SPICTL) = R0;

R0 = dm(SPICTL);

2. Add sufficient

grams need to add ten

example code below.

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

(buffer hang disable) bit for that peripheral is set

). The read forces the write to occur as

/* disable SPI */

/* dummy read, occurs only after

instructions after a write. In the worst case pro-

instructions after a write as shown in the

I/O Processor