Interrupt Force & Clear Register (Ifc); Interrupt Latency - Analog Devices adsp-2100 Manual

3 Program Control
3.4.2.4 Interrupt Force & Clear Register (IFC)
IFC is a write-only register that allows the forcing and clearing of edge-
sensitive interrupts in software. An interrupt is forced or cleared under
program control by setting the force or clear bit corresponding to the
desired interrupt. After the force or clear bit is set, there is one cycle of
latency before the interrupt is actually forced or cleared (except for the
timer interrupt on the ADSP-2101/2105/2111/2115 processors).
Edge-sensitive interrupts can be forced by setting the appropriate force bit
in IFC. This causes the interrupt to be serviced once, unless masked. An
external interrupt must be edge-sensitive (as determined by ICNTL) to be
forced. The timer, SPORT, and analog ADC/DAC interrupts also behave
like edge-sensitive interrupts and can be masked, cleared and forced.
Pending edge-sensitive interrupts can be cleared by setting the
appropriate clear bit in IFC. Edge-triggered interrupts are cleared
automatically when the corresponding interrupt service routine is called.
Specific bit definitions for each processor's IFC register are given in
Appendix E, "Control/Status Registers." The IFC registers of the ADSP-
2111, ADSP-2171, and ADSP-21msp58 processors do not include force/
clear bits for Host Interface Port interrupts; HIP interrupts cannot be
forced or cleared in software.
3.4.3

Interrupt Latency

For the timer, , SPORT, HIP, and analog interface interrupts, the
IRQx
latency from when an interrupt occurs to when the first instruction of the
service routine is executed is at least three full cycles. This is shown in
Figure 3.2. Two cycles are required to synchronize the interrupt internally,
assuming that setup and hold times are met (for the input pins).
IRQx
Since interrupts are only serviced on instruction boundaries, the
instruction(s) executed during these two cycles must be fully completed,
including any extra cycles inserted due to Bus Request/Bus Grant or
memory wait states, before execution continues.
The third cycle of latency is needed to fetch the first instruction stored at
the interrupt vector location. During this cycle, the processor executes a
NOP instead of the instruction that would normally have been executed.
On the next cycle, execution continues at the first instruction of the
interrupt service routine. The address of the aborted instruction is pushed
onto the PC stack; it will be fetched when the interrupt service routine is
completed.
3 – 18