Analog Devices ADSP-BF53x Blackfin Reference page 13

Instruction Test Registers ............................................................ 6-19
ITEST_COMMAND Register ............................................... 6-21
ITEST_DATA1 Register ........................................................ 6-22
ITEST_DATA0 Register ........................................................ 6-23
L1 Data Memory ........................................................................ 6-24
DMEM_CONTROL Register ............................................... 6-24
L1 Data SRAM ..................................................................... 6-27
L1 Data Cache ...................................................................... 6-29
Example of Mapping Cacheable Address Space .................. 6-30
Data Cache Access ............................................................ 6-33
Cache Write Method ......................................................... 6-35
IPRIO Register and Write Buffer Depth ............................ 6-35
Data Cache Control Instructions ....................................... 6-37
Data Cache Invalidation .................................................... 6-38
Data Test Registers ...................................................................... 6-38
DTEST_COMMAND Register ............................................. 6-39
DTEST_DATA1 Register ...................................................... 6-41
DTEST_DATA0 Register ...................................................... 6-42
On-chip Level 2 (L2) Memory .................................................... 6-43
On-chip L2 Bank Access ........................................................ 6-43
Latency ................................................................................. 6-44
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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