M
1
6
C
2 /
9
G
o r
u
p
2
16.4.5 Bit 7: I
The TISS bit selects the input level of the SCL and SDA pins for the multi-master I
When the TISS bit is set to 1, the P2
A reset signal to I
Figure 16.10 The timing of reset to the I
R
e
. v
1
1 .
2
M
r a
3 .
, 0
2
0
0
7
R
E
J
0
9
B
0
1
0
1
0 -
1
1
2
C bus Interface Pin Input Level Select Bit (TISS)
and P2
0
Write 1 to IHR bit
IHR bit
2
C bus interface circuit
page 268
f o
4
5
8
become the SMBus input level.
1
2.5 V
IIC
2
C bus interface circuit
16. MULTI-MASTER I
2
C bus interface.
cycles
2
C bus INTERFACE