Caution On Period Setting; Conflict Between Tcnt Write And Clear Operations; Figure 18.71 Conflict Between Tcnt Write And Clear Operations - Renesas HD6417641 Hardware Manual

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.3

Caution on Period Setting

When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
Pφ
f =
(N + 1)
Where f : Counter frequency
Pφ : Peripheral clock operating frequency
N : TGR set value
18.7.4

Conflict between TCNT Write and Clear Operations

If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed.
Figure 18.71 shows the timing in this case.
Pφ
Address
Write signal
Counter clear
signal
TCNT

Figure 18.71 Conflict between TCNT Write and Clear Operations

Rev. 4.00 Sep. 14, 2005 Page 628 of 982
REJ09B0023-0400
TCNT write cycle
T1 T2
TCNT address
N H'0000