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Section 12 8-Bit Timer (TMR)
12.9
Usage Notes
12.9.1
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T
12.13, clearing takes priority and the counter write is not performed.
φ
Address
Internal write signal
Counter clear signal
TCNT
Figure 12.13 Conflict between TCNT Write and Clear
12.9.2
Conflict between TCNT Write and Count-Up
If a count-up occurs during the T
counter write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT
Figure 12.14 Conflict between TCNT Write and Count-Up
Rev. 1.00 May 09, 2008 Page 344 of 954
REJ09B0462-0100
state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T 1
TCNT address
N
state of a TCNT write cycle as shown in figure 12.14, the
2
TCNT write cycle by CPU
T
1
TCNT address
N
Counter write data
T 2
H'00
T
2
M
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