Usage Notes; Conflict Between Tcnt Write And Counter Clear; Conflict Between Tcnt Write And Count-Up - Renesas H8S/2100 Series Hardware Manual

13.9

Usage Notes

13.9.1

Conflict between TCNT Write and Counter Clear

If a counter clear signal is generated during the T
13.13, clearing takes priority and the counter write is not performed.
φ
Address
Internal write signal
Counter clear signal
TCNT
Figure 13.13 Conflict between TCNT Write and Clear
13.9.2

Conflict between TCNT Write and Count-Up

If a count-up occurs during the T
counter write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT
Figure 13.14 Conflict between TCNT Write and Count-Up
state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T 1
TCNT address
N
state of a TCNT write cycle as shown in figure 13.14, the
2
TCNT write cycle by CPU
T
1
TCNT address
N
Counter write data
Section 13 8-Bit Timer (TMR)
T 2
H'00
T
2
M
Rev. 1.00 Apr. 28, 2008 Page 385 of 994
REJ09B0452-0100