Caution On Cycle Setting; Conflict Between Tcnt Write And Clear Operations - Renesas H8SX/1650 Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.3

Caution on Cycle Setting

When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
P
f
(N 1)
f: Counter frequency
P : Operating frequency
N: TGR set value
9.9.4

Conflict between TCNT Write and Clear Operations

If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 9.46 shows the timing in this case.
P
Address
Write
Counter clear
signal
TCNT
Figure 9.46 Conflict between TCNT Write and Clear Operations
Rev.2.00 Jun. 28, 2007 Page 382 of 666
REJ09B0311-0200
TCNT write cycle
T T
1 2
TCNT address
N H'0000