Contention Between Tcnt Write And Clear Operations; Figure 10.45 Contention Between Tcnt Write And Clear Operations - Renesas H8S Series Hardware Manual

Where f : Counter frequency
φ : Operating frequency
N : TGR set value
10.9.4

Contention between TCNT Write and Clear Operations

If the counter clear signal is generated in the T
precedence and the TCNT write is not performed.
Figure 10.45 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT

Figure 10.45 Contention between TCNT Write and Clear Operations

Section 10 16-Bit Timer Pulse Unit (TPU)
state of a TCNT write cycle, TCNT clearing takes
2
TCNT write cycle
T T
1 2
TCNT address
N H'0000
Rev. 6.00 Mar 15, 2006 page 235 of 570
REJ09B0211-0600