Usage Notes; Contention Between Tcnt Write And Clear - Renesas H8/3067 Series User Manual

10.7

Usage Notes

Note that the following kinds of contention can occur in 8-bit timer operation.
10.7.1

Contention between TCNT Write and Clear

If a timer counter clear signal occurs in the T
takes priority and the write is not performed. Figure 10.18 shows the timing in this case.
φ
Address bus
Internal write signal
Counter clear signal
TCNT
Figure 10.18 Contention between TCNT Write and Clear
state of a TCNT write cycle, clearing of the counter
3
TCNT write cycle
T T
1 2
TCNT address
N
Rev. 4.00 Jan 26, 2006 page 425 of 938
Section 10 8-Bit Timers
T
3
H'00
REJ09B0276-0400