Usage Notes; Conflict Between Tcnt Write And Clear; Table 13.4 Interrupt Sources Of 8-Bit Timers Tmr_0, Tmr_1, Tmr_Y, And Tmr_X - Renesas H8S/2158 User Manual

Table 13.4 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X

Channel Name Interrupt Source
TMR_X CMIAX TCORA_X compare-match
CMIBX TCORB_X compare-match
OVIX TCNT_X overflow
ICIX Input capture
TMR_0 CMIA0 TCORA_0 compare-match
CMIB0 TCORB_0 compare-match
OVI0 TCNT_0 overflow
TMR_1 CMIA1 TCORA_1 compare-match
CMIB1 TCORB_1 compare-match
OVI1 TCNT_1 overflow
TMR_Y CMIAY TCORA_Y compare-match
CMIBY TCORB_Y compare-match
OVIY TCNT_Y overflow
13.9

Usage Notes

13.9.1

Conflict between TCNT Write and Clear

If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure
13.14, clearing takes priority, so that the counter is cleared and the write is not performed.
Section 13 8-Bit Timer (TMR)
Interrupt DTC
Flag Activation
CMFA Possible
CMFB Possible
OVF Not possible
ICF Not possible
CMFA Possible
CMFB Possible
OVF Not possible
CMFA Possible
CMFB Possible
OVF Not possible
CMFA Possible
CMFB Possible
OVF Not possible
Rev. 3.00 Jan 25, 2006 page 339 of 872
Interrupt
Priority
High
Low
REJ09B0286-0300