18.7.17 Conflict Between Tcnt Write And Overflow/Underflow; Figure 18.83 Conflict Between Overflow And Counter Clearing; Figure 18.84 Conflict Between Tcnt Write And Overflow - Renesas HD6417641 Hardware Manual

Pφ
TCNT input
clock
TCNT
Counter clear
signal
TGF
TCFV

Figure 18.83 Conflict between Overflow and Counter Clearing

18.7.17 Conflict between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 18.84 shows the operation timing when there is conflict between TCNT write and
overflow.
Pφ
Address
Write signal
TCNT
TCFV flag

Figure 18.84 Conflict between TCNT Write and Overflow

H'FFFF
Disabled
TCNT write cycle
T1
TCNT address
H'FFFF
Section 18 Multi-Function Timer Pulse Unit (MTU)
H'0000
T2
TCNT write data
M
Rev. 4.00 Sep. 14, 2005 Page 639 of 982
REJ09B0023-0400