10.9.12 Contention Between Tcnt Write And Overflow/Underflow; 10.9.13 Multiplexing Of I/O Pins; 10.9.14 Interrupts In Module Stop Mode; Figure 10.53 Contention Between Tcnt Write And Overflow - Renesas H8S Series Hardware Manual

10.9.12 Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 10.53 shows the operation timing when there is contention between TCNT write and
overflow.
φ
Address
Write signal
TCNT
TCFV flag

Figure 10.53 Contention between TCNT Write and Overflow

10.9.13 Multiplexing of I/O Pins

In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.

10.9.14 Interrupts in Module Stop Mode

If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
Section 10 16-Bit Timer Pulse Unit (TPU)
state of a TCNT write cycle, and
2
TCNT write cycle
T T
1 2
TCNT address
H'FFFF
Prohibited
Rev. 6.00 Mar 15, 2006 page 243 of 570
TCNT write data
M
REJ09B0211-0600