Contention Between Tcnt Write And Overflow/Underflow; Cautions On Transition From Normal Operation Or Pwm Mode 1; To Reset-Synchronized Pwm Mode; Output Level In Complementary Pwm Mode And Reset-Synchronized Pwm Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.18

Contention between TCNT Write and Overflow/Underflow

If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT
write takes precedence and the TCFV/TCFU flag in TSR is not set.
Figure 10.112 shows the operation timing when there is contention between TCNT write and overflow.
Figure 10.112 Contention between TCNT Write and Overflow
10.7.19

Cautions on Transition from Normal Operation or PWM Mode 1

to Reset-Synchronized PWM Mode

When making a transition from channel 3 or 4 normal operation or PWM mode 1 to reset-synchronized PWM mode, if
the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-level
state, followed by the transition to reset-synchronized PWM mode and operation in that mode, the initial pin output will
not be correct.
When making a transition from normal operation to reset-synchronized PWM mode, write H'11 to registers TIORH_3,
TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of
H'00 before making the mode transition.
When making a transition from PWM mode 1 to reset-synchronized PWM mode, first switch to normal operation, then
initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-
synchronized PWM mode.
10.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM
Mode
When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform
output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of
complementary PWM mode or reset-synchronized PWM mode, TIOR should be set to H'00.
10.7.21

Interrupts in Module Standby Mode

If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt
source or the direct memory access controller activation source. Interrupts should therefore be disabled before entering
module standby mode.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
TCNT write cycle
T1
P0φ
TCNT address
Address
Write signal
TCNT
H'FFFF
TCFV flag
10. Multi-Function Timer Pulse Unit 2
T2
TCNT write data
M
Disabled
10-151