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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.3
Conflict between TCNT Write and Clear Operations
If the counter clear signal is generated in the T
precedence and the TCNT write is not performed. Figure 10.44 shows the timing in this case.
φ
Address
Write signal
Counter clear
signal
TCNT
Figure 10.44 Conflict between TCNT Write and Clear Operations
10.8.4
Conflict between TCNT Write and Increment Operations
If incrementing occurs in the T
and TCNT is not incremented. Figure 10.45 shows the timing in this case.
φ
Address
Write signal
TCNT input
clock
TCNT
Figure 10.45 Conflict between TCNT Write and Increment Operations
Rev. 1.00 May 09, 2008 Page 284 of 954
REJ09B0462-0100
state of a TCNT write cycle, TCNT clearing takes
2
TCNT write cycle
T1
TCNT address
N
state of a TCNT write cycle, the TCNT write takes precedence
2
TCNT write cycle
T1
TCNT address
N
TCNT write data
T2
H'0000
T2
M
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