Timing Of Imfa To Imfd Setting At Input Capture; Timing Of Status Flag Clearing; Figure 12.22 Timing Of Imfa To Imfd Flag Setting At Input Capture; Figure 12.23 Timing Of Status Flag Clearing By Cpu - Renesas H8 Series Hardware Manual

Section 12 Timer W
12.5.7

Timing of IMFA to IMFD Setting at Input Capture

If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
φ
Input capture
signal
TCNT
GRA to GRD
IMFA to IMFD
IRRTW

Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture

12.5.8

Timing of Status Flag Clearing

When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
φ
Address
Write signal
IMFA to IMFD
IRRTW

Figure 12.23 Timing of Status Flag Clearing by CPU

Rev. 3.00 Sep. 14, 2006 Page 186 of 408
REJ09B0105-0300
N
TSRW write cycle
T1 T2
TSRW address
N