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Renesas SH7706 Series Microcontrollers Manuals
Manuals and User Guides for Renesas SH7706 Series Microcontrollers. We have
1
Renesas SH7706 Series Microcontrollers manual available for free PDF download: Hardware Manual
Renesas SH7706 Series Hardware Manual (749 pages)
Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.52 MB
Table of Contents
Configuration of this Manual
4
General Precautions on Handling of Product
3
Table of Contents
4
Preface
5
Table of Contents
23
Contents
23
List of Registers
34
Electrical Characteristics
41
Section 1 Overview
49
Feature
49
Block Diagram
51
Figure 1.1 SH7706 Block Diagram
51
Pin Assignment
52
Figure 1.2 Pin Assignment (FP-176C)
52
Index
52
Figure 1.3 Pin Assignment (TBP-208A)
53
Pin Function
54
Section 2 CPU
61
Register Description
61
Privileged Mode and Banks
61
Figure 2.1 Register Configuration
62
Section 2 CPU
62
General Registers
63
Figure 2.2 General Registers
63
Table 2.1 Initial Register Values
63
System Registers
64
Figure 2.3 System Registers
64
Control Registers
65
Figure 2.4 Control Registers
65
Data Formats
68
Data Format in Registers
68
Data Format in Memory
68
Instruction Features
69
Execution Environment
69
Figure 2.5 Data Format in Memory
69
Addressing Modes
71
Table 2.2 Addressing Modes and Effective Addresses
71
Instruction Formats
75
Table 2.3 Instruction Formats
75
Instruction Set
78
Instruction Set Classified by Function
78
Table 2.4 Classification of Instructions
78
Table 2.5 Data Transfer Instructions
82
Table 2.6 Arithmetic Instructions
84
Table 2.7 Logic Operation Instructions
87
Table 2.8 Shift Instructions
88
Table 2.9 Branch Instructions
89
Table 2.10 System Control Instructions
90
Instruction Code Map
94
Table 2.11 Instruction Code Map
94
Processor States and Processor Modes
97
Processor States
97
Processor Modes
98
Figure 2.6 Processor State Transitions
98
Section 3 Memory Management Unit (MMU)
99
Role of MMU
99
Figure 3.1 MMU Functions
100
This Lsi's MMU
101
Figure 3.2 Virtual Address Space Mapping
102
Register Description
104
Page Table Entry Register High (PTEH)
105
Page Table Entry Register Low (PTEL)
105
The Translation Table Base Register (TTB)
106
The TLB Exception Address Register (TEA)
106
MMU Control Register (MMUCR)
106
TLB Functions
108
Configuration of the TLB
108
Figure 3.3 Overall Configuration of the TLB
108
Figure 3.4 Virtual Address and TLB Structure
109
Avoiding
109
TLB Indexing
110
Figure 3.5 TLB Indexing (IX = 1)
110
TLB Address Comparison
111
Figure 3.6 TLB Indexing (IX = 0)
111
Figure 3.7 Objects of Address Comparison
112
Page Management Information
113
Table 3.1 Access States Designated by D, C, and PR Bits
113
MMU Functions
114
MMU Hardware Management
114
MMU Software Management
114
MMU Instruction (LDTLB)
115
Figure 3.8 Operation of LDTLB Instruction
115
Avoiding Synonym Problems
116
Figure 3.9 Synonym Problem
117
MMU Exceptions
118
TLB Miss Exception
118
TLB Protection Violation Exception
119
TLB Invalid Exception
120
Initial Page Write Exception
121
Figure 3.10 MMU Exception Generation Flowchart
122
Processing Flow in Event of MMU Exception (same Processing Flow for CPU Address Error)
123
Figure 3.11 MMU Exception Signals in Instruction Fetch
123
Figure 3.12 MMU Exception Signals in Data Access
124
Configuration of the Memory-Mapped TLB
125
Address Array
125
Data Array
125
Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access
126
Usage Examples
127
Usage Note
127
Use of Instructions Manipulating MD and BL Bits in SR
127
Use of TLB
128
Section 4 Exception Processing
129
Exception Processing Function
129
Exception Processing Flow
129
Exception Processing Vector Addresses
130
Figure 4.1 Vector Addresses
130
Table 4.1 Exception Event Vectors
130
Acceptance of Exceptions
131
Figure 4.2 Example of Acceptance Order of General Exceptions
132
Exception Codes
133
Table 4.2 Exception Codes
133
Exception Request and BL Bit
134
Returning from Exception Processing
134
Register Description
135
Exception Event Register (EXPEVT)
135
Interrupt Event Register (INTEVT)
136
Interrupt Event Register 2 (INTEVT2)
136
TRAPA Exception Register (TRA)
137
Operation
137
Reset
137
Interrupts
138
General Exceptions
138
Individual Exception Operations
139
Resets
139
General Exceptions
140
Table 4.3 Types of Reset
140
Interrupts
143
Usage Note
145
Section 5 Cache
147
Feature
147
Cache Structure
147
Figure 5.1 Cache Structure
147
Table 5.1 LRU and Way Replacement
148
Register Description
149
Cache Control Register (CCR)
149
Cache Control Register 2 (CCR2)
150
Table 5.2 Way to be Replaced When Cache Miss Occurs During PREF Instruction
151
Table 5.3 Way to be Replaced When Cache Miss Occurs During Execution of Instruction Other than PREF Instruction
152
Table 5.4 LRU and Way Replacement (When W2LOCK = 1)
152
Table 5.5 LRU and Way Replacement (When W3LOCK = 1)
152
Table 5.6 LRU and Way Replacement (When W2LOCK = 1 and W3LOCK = 1)
152
Operation
153
Searching the Cache
153
Read Access
154
Figure 5.2 Cache Search Scheme (Normal Mode)
154
Prefetch Operation
155
Write Access
155
Write-Back Buffer
155
Figure 5.3 Write-Back Buffer Configuration
155
Coherency of Cache and External Memory
156
Memory-Mapped Cache
156
Address Array
156
Data Array
157
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
158
Usage Examples
159
Section 6 Interrupt Controller (INTC)
161
Feature
161
Figure 6.1 INTC Block Diagram
162
Input/Output Pin
163
Interrupt Sources
163
NMI Interrupts
163
Table 6.1 Pin Configuration
163
IRQ Interrupt
164
IRL Interrupts
165
Figure 6.2 Example of IRL Interrupt Connection
165
Table 6.2 IRL3 to IRL0 Pins and Interrupt Levels
165
On-Chip Peripheral Module Interrupts
166
Interrupt Exception Processing and Priority
167
Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode)
167
Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode)
169
Register Description
171
Table 6.5 Interrupt Level and INTEVT Code
171
Interrupt Priority Registers a to E (IPRA to IPRE)
172
Table 6.6 Interrupt Request Sources and IPRA to IPRE
172
Interrupt Control Register 0 (ICR0)
173
Interrupt Control Register 1 (ICR1)
174
Interrupt Request Register 0 (IRR0)
177
Interrupt Request Register 1 (IRR1)
179
Interrupt Request Register 2 (IRR2)
180
Operation
181
Interrupt Sequence
181
Figure 6.3 Interrupt Operation Flowchart
182
Multiple Interrupts
183
Interrupt Response Time
183
Table 6.7 Interrupt Response Time
184
Figure 6.4 Example of Pipeline Operations When IRL Interrupt Is Accepted
186
Section 7 User Break Controller
187
Feature
187
Figure 7.1 Block Diagram of User Break Controller
188
Register Description
189
Break Address Register a (BARA)
189
Break Address Mask Register a (BAMRA)
190
Break Bus Cycle Register a (BBRA)
190
Break Address Register B (BARB)
192
Break Address Mask Register B (BAMRB)
192
Break Data Register B (BDRB)
192
Break Data Mask Register B (BDMRB)
193
Break Bus Cycle Register B (BBRB)
193
Break Control Register (BRCR)
195
Execution Times Break Register (BETR)
198
Branch Source Register (BRSR)
199
Branch Destination Register (BRDR)
200
Break ASID Register a (BASRA)
200
Break ASID Register B (BASRB)
201
Operation
201
Flow of the User Break Operation
201
Break on Instruction Fetch Cycle
202
Break by Data Access Cycle
202
Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions
202
Sequential Break
203
Value of Saved Program Counter
203
PC Trace
204
Usage Examples
206
Usage Note
210
Section 8 Bus State Controller (BSC)
211
Feature
211
Figure 8.1 BSC Functional Block Diagram
212
Input/Output Pin
213
Table 8.1 Pin Configuration
213
Area Overview
214
Figure 8.2 Corresponding to Logical Address Space and Physical Address Space
215
Table 8.2 Physical Address Space Map
216
Figure 8.3 Physical Space Allocation
217
Table 8.3 Correspondence between External Pins (MD4 and MD3) and Memory Size
217
PCMCIA Support
218
Figure 8.4 PCMCIA Space Allocation
218
Table 8.4 PCMCIA Interface Characteristics
218
Table 8.5 PCMCIA Support Interface
219
Register Description
221
Bus Control Register 1 (BCR1)
222
Bus Control Register 2 (BCR2)
225
Wait State Control Register 1 (WCR1)
227
Wait State Control Register 2 (WCR2)
230
Table 8.6 Area 6 Wait Control (Normal Memory I/F)
232
Table 8.7 Area 5 Wait Control (Normal Memory I/F)
232
Table 8.8 Area 4 Wait Control
233
Table 8.9 Area 0 Wait Control
233
Individual Memory Control Register (MCR)
234
PCMCIA Control Register (PCR)
238
Table 8.10 Area 6 Wait Control (PCMCIA I/F)
240
Synchronous DRAM Mode Register (SDMR)
241
Refresh Timer Control/Status Register (RTCSR)
241
Refresh Timer Counter (RTCNT)
244
Refresh Time Constant Register (RTCOR)
244
Refresh Count Register (RFCR)
245
Operation
245
Endian/Access Size and Data Alignment
245
Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment
246
Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment
246
Table 8.13 8-Bit External Device/Big Endian Access and Data Alignment
247
Table 8.14 32-Bit External Device/Little Endian Access and Data Alignment
248
Table 8.15 16-Bit External Device/Little Endian Access and Data Alignment
248
Table 8.16 8-Bit External Device/Little Endian Access and Data Alignment
249
Description of Areas
250
Basic Interface
253
Figure 8.5 Basic Timing of Basic Interface
254
Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection
255
Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection
256
Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection
256
Figure 8.9 Basic Interface Wait Timing (Software Wait Only)
257
Figure 8.10 Basic Interface Wait State Timing
258
Synchronous DRAM Interface
259
Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)
260
Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width)
261
Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output
262
Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))
263
Figure 8.13 Basic Timing for Synchronous DRAM Burst Read
264
Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing
265
Figure 8.15 Basic Timing for Synchronous DRAM Single Read
266
Figure 8.16 Basic Timing for Synchronous DRAM Burst Write
267
Figure 8.17 Basic Timing for Synchronous DRAM Single Write
268
Figure 8.18 Burst Read Timing (no Precharge)
271
Figure 8.19 Burst Read Timing (same Row Address)
272
Figure 8.20 Burst Read Timing (Different Row Addresses)
273
Figure 8.21 Burst Write Timing (no Precharge)
274
Figure 8.22 Burst Write Timing (same Row Address)
275
Figure 8.23 Burst Write Timing (Different Row Addresses)
276
Figure 8.24 Auto-Refresh Operation
277
Figure 8.25 Synchronous DRAM Auto-Refresh Timing
278
Figure 8.26 Synchronous DRAM Self-Refresh Timing
279
Figure 8.27 Synchronous DRAM Mode Write Timing
281
Burst ROM Interface
282
Figure 8.28 Burst ROM Wait Access Timing
283
PCMCIA Interface
284
Figure 8.29 Burst ROM Basic Access Timing
284
Figure 8.30 PCMCIA Space Allocation
285
Figure 8.31 Example of PCMCIA Interface
286
Figure 8.32 Basic Timing for PCMCIA Memory Card Interface
287
Figure 8.33 Wait Timing for PCMCIA Memory Card Interface
288
Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access
289
Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access
290
Figure 8.36 Basic Timing for PCMCIA I/O Card Interface
292
Figure 8.37 Wait Timing for PCMCIA I/O Card Interface
293
Figure 8.38 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface
294
Waits between Access Cycles
295
Bus Arbitration
296
Figure 8.39 Waits between Access Cycles
296
Bus Pull-Up
297
Figure 8.40 Pins A25 to A0 Pull-Up Timing
297
Figure 8.41 Pins D31 to D0 Pull-Up Timing (Read Cycle)
298
Figure 8.42 Pins D31 to D0 Pull-Up Timing (Write Cycle)
298
Section 9 Direct Memory Access Controller (DMAC)
299
Feature
299
Figure 9.1 DMAC Block Diagram
301
Input/Output Pin
302
Register Description
302
Table 9.1 Pin Configuration
302
DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3)
303
DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)
303
DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)
304
DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)
304
DMA Operation Register (DMAOR)
311
Operation
313
DMA Transfer Flow
313
Figure 9.2 DMAC Transfer Flowchart
314
DMA Transfer Requests
315
Table 9.2 Selecting External Request Modes with the RS Bits
315
Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit
316
Channel Priority
317
Figure 9.3 Round-Robin Mode
318
Figure 9.4 Changes in Channel Priority in Round-Robin Mode
319
DMA Transfer Types
320
Table 9.4 Supported DMA Transfers
320
Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode
321
Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
322
Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-Byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory)
323
Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-Byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary Memory)
323
Figure 9.9 Operation in the Indirect Address Mode in the Dual Address Mode (When the External Memory Space Has a 16-Bit Width)
325
Figure 9.10 Example of Transfer Timing in the Indirect Address Mode in the Dual Address Mode
326
Figure 9.11 Data Flow in the Single Address Mode
327
Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode
328
Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode (16-Byte Transfer, External Memory Space (Ordinary Memory) → External Device with DACK)
329
Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode
330
Figure 9.15 DMA Transfer Example in the Burst Mode
330
Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category
331
Number of Bus Cycle States and DREQ Pin Sampling Timing
332
Figure 9.16 Bus State When Multiple Channels Are Operating (Priority Level Is Round-Robin Mode)
332
Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles)
334
Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles)
334
Figure 9.19 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles)
334
Figure 9.20 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles, DREQ Input Delayed)
335
Figure 9.21 Cycle-Steal Mode, Edge Input (CPU Access: 2 Cycles)
335
Figure 9.22 Burst Mode, Level Input
335
Source Address Reload Function
336
Figure 9.23 Burst Mode, Edge Input
336
Figure 9.24 Source Address Reload Function Diagram
336
Figure 9.25 Timing Chart of Source Address Reload Function
337
DMA Transfer Ending Conditions
338
Compare Match Timer (CMT)
340
Feature
340
Figure 9.26 CMT Block Diagram
340
Register Description
341
Operation
343
Figure 9.27 Counter Operation
343
Figure 9.28 Count Timing
344
Figure 9.29 CMF Set Timing
345
Figure 9.30 Timing of CMF Clear by the CPU
345
Examples of Use
346
Example of DMA Transfer between A/D Converter and External Memory (Address Reload On)
346
Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D
346
(Indirect Address On)
347
Table 9.7 Values in the DMAC after the Fourth Transfer Ends
347
Table 9.8 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter
348
Cautions
349
Section 10 Clock Pulse Generator (CPG)
351
Feature
351
Figure 10.1 Block Diagram of Clock Pulse Generator
352
Input/Output Pin
354
Clock Operating Modes
354
Table 10.1 Clock Pulse Generator Pins and Functions
354
Table 10.2 Clock Operating Modes
355
Table 10.3 Available Combination of Clock Mode and FRQCR Values
356
Register Description
358
Frequency Control Register (FRQCR)
358
Operation
360
Changing the Multiplication Rate
360
Changing the Division Ratio
360
Usage Note
361
Figure 10.2 Points for Attention When Using Crystal Oscillator
361
Figure 10.3 Points for Attention When Using PLL Oscillator Circuit
362
Section 11 Watchdog Timer (WDT)
363
Feature
363
Figure 11.1 Block Diagram of the WDT
363
Register Description
364
Watchdog Timer Counter (WTCNT)
364
Watchdog Timer Control/Status Register (WTCSR)
364
Notes on Register Access
366
Operation
367
Canceling Software Standbys
367
Figure 11.2 Writing to WTCNT and WTCSR
367
Changing the Frequency
368
Using Watchdog Timer Mode
368
Using Interval Timer Mode
369
Section 12 Timer Unit (TMU)
371
Feature
371
Figure 12.1 TMU Block Diagram
372
Input/Output Pin
373
Register Description
373
Table 12.1 Pin Configuration
373
Timer Output Control Register (TOCR)
374
Timer Start Register (TSTR)
375
Timer Control Registers 0 to 2 (TCR_0 to TCR_2)
376
Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)
379
Timer Counters 0 to 2 (TCNT_0 to TCNT_2)
380
Input Capture Register 2 (TCPR_2)
380
Operation
380
Counter Operation
381
Figure 12.2 Setting the Count Operation
381
Figure 12.3 Auto-Reload Count Operation
382
Figure 12.4 Count Timing When Internal Clock Is Operating
382
Figure 12.5 Count Timing When External Clock Is Operating (both Edges Detected)
383
Figure 12.6 Count Timing When On-Chip RTC Clock Is Operating
383
Input Capture Function
384
Figure 12.7 Operation Timing When Using the Input Capture Function (Using TCLK Rising Edge)
384
Interrupts
385
Status Flag Set Timing
385
Status Flag Clear Timing
385
Figure 12.8 UNF Set Timing
385
Figure 12.9 Status Flag Clear Timing
385
Interrupt Sources and Priorities
386
Usage Note
386
Writing to Registers
386
Reading Registers
386
Table 12.2 TMU Interrupt Sources
386
Section 13 Realtime Clock (RTC)
387
Feature
387
Figure 13.1 RTC Block Diagram
388
Input/Output Pin
389
Register Description
389
Table 13.1 RTC Pin Configuration
389
64-Hz Counter (R64CNT)
390
Second Counter (RSECCNT)
391
Minute Counter (RMINCNT)
391
Hour Counter (RHRCNT)
392
Day of the Week Counter (RWKCNT)
392
Date Counter (RDAYCNT)
393
Month Counter (RMONCNT)
394
Year Counter (RYRCNT)
394
Second Alarm Register (RSECAR)
395
Minute Alarm Register (RMINAR)
395
Hour Alarm Register (RHRAR)
396
Day of the Week Alarm Register (RWKAR)
397
Date Alarm Register (RDAYAR)
398
Month Alarm Register (RMONAR)
399
RTC Control Register 1 (RCR1)
400
RTC Control Register 2 (RCR2)
402
RTC Operation
404
Initial Settings of Registers after Power-On
404
Setting the Time
404
Figure 13.2(A) Setting the Time
405
Figure 13.2(B) Setting the Time
405
Reading the Time
406
Figure 13.3 Reading the Time
406
Alarm Function
407
Figure 13.4 Using the Alarm Function
407
Crystal Oscillator Circuit
408
Figure 13.5 Example of Crystal Oscillator Circuit Connection
408
Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values)
408
Usage Note
409
Register Writing During RTC Count
409
Use of Realtime Clock (RTC) Periodic Interrupts
409
Figure 13.6 Using Periodic Interrupt Function
409
Timing for Setting ADJ Bit in RCR2
410
Section 14 Serial Communication Interface (SCI)
411
Feature
411
Figure 14.1 SCI Block Diagram
412
Figure 14.2 SCPT[1]/SCK0 Pin
413
Figure 14.3 Scpt[0]/Txd0 Pin
414
Figure 14.4 Scpt[0]/Rxd0 Pin
414
Input/Output Pin
415
Register Description
415
Table 14.1 SCI Pins
415
Receive Shift Register (SCRSR)
416
Receive Data Register (SCRDR)
416
Transmit Shift Register (SCTSR)
416
Transmit Data Register (SCTDR)
416
Serial Mode Register (SCSMR)
417
Serial Control Register (SCSCR)
420
Serial Status Register (SCSSR)
424
SC Port Control Register (SCPCR)
429
SC Port Data Register (SCPDR)
430
Bit Rate Register (SCBRR)
431
Table 14.2 SCSMR Settings
431
Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode
432
Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode
435
Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
436
Table 14.6 Maximum Bit Rates During External Clock Input (Asynchronous Mode)
437
Table 14.7 Maximum Bit Rates During External Clock Input (Clock Synchronous Mode)
437
Operation
438
Table 14.8 Serial Mode Register Settings and SCI Communication Formats
439
Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection
439
Operation in Asynchronous Mode
440
Figure 14.5 Data Format in Asynchronous Communication
440
Table 14.10 Serial Communication Formats (Asynchronous Mode)
441
Figure 14.6 Output Clock and Serial Data Timing (Asynchronous Mode)
442
Figure 14.7 Sample Flowchart for SCI Initialization
443
Figure 14.8 Sample Flowchart for Transmitting Serial Data
444
Figure 14.9 SCI Transmit Operation in Asynchronous Mode
446
Figure 14.10 Sample Flowchart for Receiving Serial Data
447
Table 14.11 Receive Error Conditions and SCI Operation
449
Multiprocessor Communication
450
Figure 14.11 SCI Receive Operation
450
Figure 14.12 Communication Among Processors Using Multiprocessor Format
451
Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data
452
Figure 14.14 SCI Multiprocessor Transmit Operation
454
Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data
455
Figure 14.16 Example of SCI Receive Operation
457
Clock Synchronous Operation
458
Figure 14.17 Data Format in Clock Synchronous Communication
458
Figure 14.18 Sample Flowchart for SCI Initialization
459
Figure 14.19 Sample Flowchart for Serial Transmitting
460
Figure 14.20 Example of SCI Transmit Operation
461
Figure 14.21 Sample Flowchart for Serial Data Receiving
462
Figure 14.22 Example of SCI Receive Operation
463
Figure 14.23 Sample Flowchart for Serial Data Transmitting/Receiving
464
SCI Interrupt Sources
465
Table 14.12 SCI Interrupt Sources
465
Usage Note
466
Table 14.13 SCSSR Status Flags and Transfer of Receive Data
466
Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode
467
Section 15 Smart Card Interface
469
Feature
469
Figure 15.1 Smart Card Interface Block Diagram
470
Input/Output Pin
471
Register Description
471
Table 15.1 Pin Configuration
471
Smart Card Mode Register (SCSCMR)
472
Serial Status Register (SCSSR)
473
Operation
475
Overview
475
Pin Connections
475
Data Format
476
Figure 15.2 Pin Connection Diagram for the Smart Card Interface
476
Figure 15.3 Data Format for Smart Card Interface
476
Register Settings
477
Table 15.2 Register Settings for the Smart Card Interface
477
Figure 15.4 Waveform of Start Character
478
Clock
479
Table 15.3 Relationship of N to CKS1 and CKS0
479
Table 15.4 Examples of Bit Rate B (Bit/S) for SCBRR Settings (N = 0)
479
Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/S) (N = 0)
480
Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
480
Data Transmission and Reception
481
Table 15.7 Register Set Values and Sckφ Pin
481
Figure 15.5 Initialization Flowchart (Example)
482
Figure 15.6 Transmission Flowchart
483
Figure 15.7 Reception Flowchart (Example)
484
Usage Note
485
Table 15.8 Smart Card Mode Operating State and Interrupt Sources
485
Figure 15.8 Receive Data Sampling Timing in Smart Card Mode
486
Figure 15.9 Retransmission in SCI Receive Mode
487
Figure 15.10 Retransmission in SCI Transmit Mode
488
Section 16 Serial Communication Interface with FIFO (SCIF)
489
Feature
489
Figure 16.1 SCIF Block Diagram
490
Figure 16.2 SCPT[3]/SCK2 Pin
491
Figure 16.3 Scpt[2]/Txd2 Pin
492
Figure 16.4 Scpt[2]/Rxd2 Pin
492
Input/Output Pin
493
Register Description
493
Table 16.1 SCIF Pins
493
Receive Shift Register 2 (SCRSR2)
494
Receive FIFO Data Register 2 (SCFRDR2)
494
Transmit Shift Register 2 (SCTSR2)
494
Transmit FIFO Data Register 2 (SCFTDR2)
494
Serial Mode Register 2 (SCSMR2)
495
Serial Control Register 2 (SCSCR2)
497
Serial Status Register 2 (SCSSR2)
500
Bit Rate Register 2 (SCBRR2)
508
Table 16.2 SCSMR2 Settings
508
Table 16.3 Bit Rates and SCBRR2 Settings
509
Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator
513
Table 16.5 Maximum Bit Rates During External Clock Input (Asynchronous Mode)
513
FIFO Control Register 2 (SCFCR2)
514
FIFO Data Count Set Register 2 (SCFDR2)
516
SC Port Control Register (SCPCR)
516
SC Port Data Register (SCPDR)
516
Operation
517
Table 16.6 SCSMR2 Settings and SCIF Communication Formats
517
Serial Operation
518
Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection
518
Table 16.8 Serial Communication Formats
518
Figure 16.5 Sample SCIF Initialization Flowchart
520
Figure 16.6 Sample Serial Transmission Flowchart
521
Figure 16.7 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit)
523
Figure 16.8 Example of Operation Using Modem Control (CTS2)
523
Figure 16.9 Sample Serial Reception Flowchart (1)
524
Figure 16.10 Sample Serial Reception Flowchart (2)
525
Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit)
527
Figure 16.12 Example of Operation Using Modem Control (RTS2)
527
SCIF Interrupts
528
Table 16.9 SCIF Interrupt Sources
528
Usage Notes
529
Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode
530
Section 17 Pin Function Controller (PFC)
533
Table 17.1 List of Multiplexed Pins
533
Register Description
536
Port a Control Register (PACR)
537
Port B Control Register (PBCR)
538
Port C Control Register (PCCR)
540
Port D Control Register (PDCR)
541
Port E Control Register (PECR)
543
Port F Control Register (PFCR)
545
Port G Control Register
547
Port H Control Register (PHCR)
548
Port J Control Register (PJCR)
550
SC Port Control Register (SCPCR)
551
Section 18 I/O Ports
555
Port a
555
Register Description
555
Figure 18.1 Port a
555
Port a Data Register (PADR)
556
Table 18.1 Read/Write Operation of the Port a Data Register (PADR)
556
Manual
556
Port B
557
Register Description
557
Figure 18.2 Port B
557
Port B Data Register (PBDR)
558
Table 18.2 Read/Write Operation of the Port B Data Register (PBDR)
558
Port C
559
Register Description
559
Figure 18.3 Port C
559
Port C Data Register (PCDR)
560
Table 18.3 Read/Write Operation of the Port C Data Register (PCDR)
560
Port D
561
Register Description
561
Figure 18.4 Port D
561
Port D Data Register (PDDR)
562
Table 18.4 Read/Write Operation of the Port D Data Register (PDDR)
562
Port E
563
Register Description
563
Figure 18.5 Port E
563
Port E Data Register (PEDR)
564
Table 18.5 Read/Write Operation of the Port E Data Register (PEDR)
564
Port F
565
Register Description
565
Figure 18.6 Port F
565
Port F Data Register (PFDR)
566
Table 18.6 Read/Write Operation of the Port F Data Register (PFDR)
566
Port G
567
Register Description
567
Figure 18.7 Port G
567
Port G Data Register
568
Table 18.7 Read/Write Operation of the Port G Data Register
568
Port H
569
Register Description
569
Figure 18.8 Port H
569
Port H Data Register (PHDR)
570
Table 18.8 Read/Write Operation of the Port H Data Register (PHDR)
570
Port J
571
Register Description
571
Figure 18.9 Port J
571
Port J Data Register (PJDR)
572
Table 18.9 Read/Write Operation of the Port J Data Register (PJDR)
572
SC Port
573
18.10.1 Register Description
573
Figure 18.10 SC Port
573
SC Port Data Register (SCPDR)
574
Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR)
575
Section 19 A/D Converter (ADC)
577
Features
577
Figure 19.1 A/D Converter Block Diagram
578
Input/Output Pin
579
Register Description
579
Table 19.1 A/D Converter Pins
579
A/D Data Registers a to D (ADDRA to ADDRD)
580
Table 19.2 Analog Input Channels and A/D Data Registers
580
A/D Control/Status Register (ADCSR)
581
A/D Control Register (ADCR)
584
Bus Master Interface
584
Figure 19.2 A/D Data Register Access Operation (Reading H'AA40)
585
Access Size of A/D Data Register
586
Word Access
586
Longword Access
586
Figure 19.3 Word Access Example
586
Figure 19.4 Longword Access Example
586
Operation
587
Single Mode (MULTI = 0)
587
Multi Mode (MULTI = 1, SCN = 0)
588
Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
588
Figure 19.6 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected)
589
Scan Mode (MULTI = 1, SCN = 1)
590
Input Sampling and A/D Conversion Time
591
Figure 19.7 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
591
Figure 19.8 A/D Conversion Timing
592
Table 19.3 A/D Conversion Time (Single Mode)
592
External Trigger Input Timing
593
Interrupt Requests
593
Definitions of A/D Conversion Accuracy
593
Figure 19.9 External Trigger Input Timing
593
Usage Note
594
Setting Analog Input Voltage
594
Figure 19.10 Definitions of A/D Conversion Accuracy
594
Processing of Analog Input Pins
595
Figure 19.11 Example of Analog Input Protection Circuit
595
Figure 19.12 Analog Input Pin Equivalent Circuit
595
Table 19.4 Analog Input Pin Ratings
595
Access Size and Read Data
596
Table 19.5 Relationship between Access Size and Read Data
596
Section 20 D/A Converter (DAC)
597
Feature
597
Figure 20.1 D/A Converter Block Diagram
597
Input/Output Pin
598
Register Description
598
D/A Data Registers 0 and 1 (DADR0 and DADR1)
598
D/A Control Register (DACR)
598
Table 20.1 D/A Converter Pins
598
Operation
600
Figure 20.2 Example of D/A Converter Operation
600
Section 21 User Debugging Interface (H-UDI)
601
Figure 21.1 H-UDI Block Diagram
601
Feature
602
Input/Output Pin
602
Table 21.1 Pin Configuraiton
602
Register Description
603
Bypass Register (SDBPR)
603
Instruction Register (SDIR)
603
Boundary Scan Register (SDBSR)
604
Table 21.2 this Lsi's Pins and Boundary Scan Register Bits
604
H-UDI Operations
609
TAP Controller
609
Figure 21.2 TAP Controller State Transitions
609
Reset Configuration
610
Table 21.3 Reset Configuration
610
H-UDI Reset
611
H-UDI Interrupt
611
Bypass
611
Using H-UDI to Recover from Sleep Mode
611
Figure 21.3 H-UDI Reset
611
Boundary Scan
612
Supported Instructions
612
Notes for Boundary Scan
613
Usage Note
613
Advanced User Debugger (AUD)
613
Section 22 Power-Down Modes
615
Table 22.1 Power-Down Modes
616
Input/Output Pin
617
Register Description
617
Standby Control Register (STBCR)
617
Table 22.2 Pin Configuration
617
Standby Control Register 2 (STBCR2)
619
Operation
621
Sleep Mode
621
Software Standby Mode
622
Table 22.3 Register States in Software Standby Mode
622
Figure 22.1 Canceling Software Standby Mode with STBCR.STBY
623
Module Standby Function
624
Problem
624
Timing of STATUS Pin Changes
626
Figure 22.2 Power-On Reset STATUS Output
626
Figure 22.3 Manual Reset STATUS Output
626
Figure 22.4 Software Standby to Interrupt STATUS Output
627
Figure 22.5 Software Standby to Power-On Reset STATUS Output
627
Figure 22.6 Software Standby to Manual Reset STATUS Output
628
Figure 22.7 Sleep to Interrupt STATUS Output
628
Figure 22.8 Sleep to Power-On Reset STATUS Output
629
Figure 22.9 Sleep to Manual Reset STATUS Output
629
Hardware Standby Function
630
Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation)
631
Figure 22.11 Hardware Standby Mode Timing (When CA Goes Low During WDT Operation on Standby Mode Cancellation)
632
Section 23 List of Registers
633
Register Address Map
633
Register Bits
639
Register States in Processing Mode
650
Section 24 Electrical Characteristics
655
Absolute Maximum Ratings
655
Table 24.1 Absolute Maximum Ratings
655
DC Characteristics
657
Table 24.2 DC Characteristics
657
Table 24.3 Permitted Output Current Values
659
AC Characteristics
660
Clock Timing
660
Table 24.4 Operating Frequency Range
660
Table 24.5 Clock Timing
660
Figure 24.1 EXTAL Clock Input Timing
662
Figure 24.2 CKIO Clock Input Timing
662
Figure 24.3 CKIO Clock Output Timing
662
Figure 24.4 Power-On Oscillation Settling Time
663
Figure 24.5 Oscillation Settling Time at Standby Return (Return by Reset)
663
Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI)
664
Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL)
664
Figure 24.8 PLL Synchronization Settling Time by Reset or NMI at the Returning from Standby Mode (Return by Reset or NMI)
665
Figure 24.9 PLL Synchronization Settling Time at the Returning from Standby Mode (Return by IRQ/IRL Interrupt)
665
Figure 24.10 PLL Synchronization Settling Time When Frequency Multiplication Rate Modified
666
Control Signal Timing
667
Table 24.6 Control Signal Timing
667
Figure 24.11 Reset Input Timing
668
Figure 24.12 Interrupt Signal Input Timing
668
Figure 24.13 IRQOUT Timing
668
Figure 24.14 Bus Release Timing
669
Figure 24.15 Pin Drive Timing at Standby
669
AC Bus Timing
670
Table 24.7 Bus Timing (Clock Modes 0/1/2/7)
670
Basic Timing
672
Figure 24.16 Basic Bus Cycle (no Wait)
672
Figure 24.17 Basic Bus Cycle (One Wait)
673
Figure 24.18 Basic Bus Cycle (External Wait)
674
Burst ROM Timing
675
Figure 24.19 Burst ROM Bus Cycle (no Wait)
675
Figure 24.20 Burst ROM Bus Cycle (Two Waits)
676
Figure 24.21 Burst ROM Bus Cycle (External Wait)
677
Synchronous DRAM Timing
678
Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
678
Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)
679
Figure 24.24 Synchronous DRAM Read Bus Cycle
680
Figure 24.25 Synchronous DRAM Read Bus Cycle
681
Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0)
682
Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1)
683
Figure 24.28 Synchronous DRAM Write Bus Cycle
684
Figure 24.29 Synchronous DRAM Write Bus Cycle
685
Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, same Row Address, CAS Latency = 1)
686
Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, same Row Address, CAS Latency = 2)
687
Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1)
688
Figure 24.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1)
689
Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, same Row Address)
690
Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0)
691
Figure 24.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1)
692
Figure 24.37 Synchronous DRAM Auto-Refresh Timing (tras = 1, TPC = 1)
693
Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0)
693
Figure 24.39 Synchronous DRAM Mode Register Write Cycle
694
PCMCIA Timing
695
Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, no Wait)
695
Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait)
696
Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, no Wait)
697
Figure 24.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3)
698
Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, no Wait)
699
Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait)
700
Figure 24.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing)
701
Peripheral Module Signal Timing
702
Table 24.8 Peripheral Module Signal Timing
702
Figure 24.47 TCLK Input Timing
703
Figure 24.48 TCLK Clock Input Timing
703
Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-On
703
Figure 24.50 SCK Input Clock Timing
703
Figure 24.51 SCI I/O Timing in Clock Synchronous Mode
704
Figure 24.52 I/O Port Timing
704
Figure 24.53 DREQ Input Timing
705
Figure 24.54 DRAK Output Timing
705
H-UDI, AUD Related Pin Timing
706
Figure 24.55 TCK Input Timing
706
Table 24.9 H-UDI, AUD Related Pin Timing
706
Figure 24.56 TRST Input Timing (Reset Hold)
707
Figure 24.57 H-UDI Data Transfer Timing
707
Figure 24.58 ASEMD0 Input Timing
707
24.3.10 A/D Converter Timing
708
Figure 24.59 AUD Timing
708
Table 24.10 A/D Converter Timing
708
Figure 24.60 External Trigger Input Timing
709
Figure 24.61 A/D Conversion Timing
709
24.3.11 AC Characteristics Measurement Conditions
710
Figure 24.62 Output Load Circuit
710
24.3.12 Delay Time Variation Due to Load Capacitance
711
Figure 24.63 Load Capacitance Vs. Delay Time
711
A/D Converter Characteristics
712
D/A Converter Characteristics
712
Table 24.11 A/D Converter Characteristics
712
Table 24.12 D/A Converter Characteristics
712
Appendix
713
Equivalent Circuits of I/O Buffer for each Pin
713
Pin Functions
717
Table B.1 Pin States During Resets, Power-Down States, and Bus-Released State
717
Pin Specifications
721
Table B.2 Pin Specifications
721
Processing of Unused Pins
725
Pin States in Access to each Address Space
726
Table B.3 Pin States (Normal Memory/Little Endian)
726
Table B.4 Pin States (Normal Memory/Big Endian)
728
Table B.5 Pin States (Burst Rom/Little Endian)
730
Table B.6 Pin States (Burst Rom/Big Endian)
732
Table B.7 Pin States (Synchronous Dram/Little Endian)
734
Table B.8 Pin States (Synchronous Dram/Big Endian)
735
Table B.9 Pin States (Pcmcia/Little Endian)
736
Table B.10 Pin States (Pcmcia/Big Endian)
738
Product Lineup
740
Package Dimensions
741
Figure D.1 Package Dimensions (FP-176C)
741
Figure D.2 Package Dimensions (TBP-208A)
742
Index
743
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