Renesas H8/36912 Series Manuals

Manuals and User Guides for Renesas H8/36912 Series. We have 3 Renesas H8/36912 Series manuals available for free PDF download: Hardware Manual, User Manual

Renesas H8/36912 Series Hardware Manual (442 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 2.49 MB

Table of Contents
11
Section 1 Overview
31
Features
31
- Section 1 Overview
  32
Figure 1.1 Internal Block Diagram of H8/36912 Group
33
Internal Block Diagram
33
Figure 1.2 Internal Block Diagram of H8/36902 Group
34
Pin Arrangement
35
Figure 1.3 Pin Arrangement of H8/36912 Group (FP-32A)
35
Figure 1.4 Pin Arrangement of H8/36902 Group (FP-32A)
36
Figure 1.5 Pin Arrangement of H8/36912 Group (FP-32D, 32P4B)
37
Figure 1.6 Pin Arrangement of H8/36902 Group (FP-32D, 32P4B)
38
Table 1.1 Pin Functions
39
Pin Functions
39
Section 2 CPU
41
Address Space and Memory Map
42
- Figure 2.1 Memory Map (1)
  42
- Section 2 CPU
  42
Figure 2.1 Memory Map (2)
43
Register Configuration
44
Data Formats
48
Instruction Set
51
Addressing Modes and Effective Address Calculation
62
Basic Bus Cycle
67
Figure 2.11 CPU Operation States
69
CPU States
69
Usage Notes
70
Table 3.1 Exception Sources and Vector Address
77
Section 3 Exception Handling
77
Exception Sources and Vector Address
77
Register Descriptions
79
Reset Exception Handling
84
Interrupt Exception Handling
85
Usage Notes
91
Section 4 Address Break
93
Figure 4.1 Block Diagram of Address Break
93
Register Descriptions
94
Operation
97
Figure 4.2 Address Break Interrupt Operation Example (1)
97
Figure 4.2 Address Break Interrupt Operation Example (2)
98
Figure 5.1 Block Diagram of Clock Pulse Generators
99
Section 5 Clock Pulse Generators
99
Features
100
Register Descriptions
101
System Clock Select Operation
105
Figure 5.7 Example of Trimming Flow for On-Chip Oscillator Frequency
110
Trimming of On-Chip Oscillator Frequency
110
Figure 5.8 Timing Chart of Trimming of On-Chip Oscillator Frequency
111
External Oscillators
112
Prescaler
113
Usage Notes
114
- Note on Resonators
  114
- Notes on Board Design
  114
- Figure 5.13 Example of Incorrect Board Design
  114
Section 6 Power-Down Modes
115
Register Descriptions
115
Mode Transitions and States of LSI
121
Operating Frequency in Active Mode
124
Direct Transition
124
Module Standby Function
125
Section 7 ROM
127
Block Configuration
127
Figure 7.1 Flash Memory Block Configuration
128
Register Descriptions
129
On-Board Programming Modes
132
Flash Memory Programming/Erasing
137
Program/Erase Protection
142
- Hardware Protection
  142
- Software Protection
  142
- Error Protection
  142
Section 8 RAM
145
Section 9 I/O Ports
147
Port 1
147
- Figure 9.1 Port 1 Pin Configuration
  147
- Port Mode Register 1 (PMR1)
  148
- Port Control Register 1 (PCR1)
  149
- Port Data Register 1 (PDR1)
  149
- Pin Functions
  150
- Port Pull-Up Control Register 1 (PUCR1)
  150
Port 2
151
- Figure 9.2 Port 2 Pin Configuration
  151
- Port Control Register 2 (PCR2)
  152
- Port Data Register 2 (PDR2)
  152
- Pin Functions
  153
Port 5
154
- Figure 9.3 Port 5 Pin Configuration
  154
- Port Control Register 5 (PCR5)
  155
- Port Mode Register 5 (PMR5)
  155
- Port Data Register 5 (PDR5)
  156
- Port Pull-Up Control Register 5 (PUCR5)
  156
- Pin Functions
  157
Port 7
158
- Port Control Register 7 (PCR7)
  158
- Figure 9.4 Port 7 Pin Configuration
  158
- Port Data Register 7 (PDR7)
  159
- Pin Functions
  159
Port 8
160
- Figure 9.5 Port 8 Pin Configuration
  160
- Port Control Register 8 (PCR8)
  161
- Port Data Register 8 (PDR8)
  161
- Pin Functions
  162
Port B
164
- Port Data Register B (PDRB)
  164
- Figure 9.6 Port B Pin Configuration
  164
- Pin Functions
  165
Port C
166
- Figure 9.7 Port C Pin Configuration
  166
- Port Control Register C (PCRC)
  167
- Port Data Register C (PDRC)
  167
- Pin Functions
  168
Figure 10.1 Block Diagram of Timer B1
169
Section 10 Timer B1
169
Features
169
Register Descriptions
170
- Timer Mode Register B1 (TMB1)
  170
- Timer Counter B1 (TCB1)
  171
- Timer Load Register B1 (TLB1)
  171
Operation
172
- Interval Timer Operation
  172
- Auto-Reload Timer Operation
  172
Table 10.1 Timer B1 Operating Modes
173
Timer B1 Operating Modes
173
Section 11 Timer V
175
Features
175
Input/Output Pins
177
Register Descriptions
177
Operation
182
Timer V Application Examples
185
Figure 11.11 Contention between TCNTV Write and Clear
187
Usage Notes
187
Figure 11.12 Contention between TCORA Write and Compare Match
188
Figure 11.13 Internal Clock Switching and TCNTV Operation
188
Section 12 Timer W
189
Features
189
Table 12.1 Timer W Functions
190
Figure 12.1 Timer W Block Diagram
191
Input/Output Pins
192
Register Descriptions
192
- Table 12.2 Pin Configuration
  192
- Timer Mode Register W (TMRW)
  193
- Timer Control Register W (TCRW)
  194
- Timer Interrupt Enable Register W (TIERW)
  195
- Timer Status Register W (TSRW)
  196
- Timer I/O Control Register 0 (TIOR0)
  198
- Timer I/O Control Register 1 (TIOR1)
  199
- General Registers a to D (GRA to GRD)
  201
- Timer Counter (TCNT)
  201
Operation
202
Operation Timing
211
Usage Notes
217
Figure 12.24 Contention between TCNT Write and Clear
218
Figure 12.25 Internal Clock Switching and TCNT Operation
218
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the same Timing
219
Figure 13.1 Block Diagram of Watchdog Timer
221
Section 13 Watchdog Timer
221
Features
221
Register Descriptions
222
Figure 13.2 Watchdog Timer Operation Example
225
Operation
225
Section 14 Serial Communication Interface 3 (SCI3)
227
Features
227
Figure 14.1 Block Diagram of SCI3
228
Input/Output Pins
229
Register Descriptions
229
Operation in Asynchronous Mode
242
Operation in Clocked Synchronous Mode
249
Multiprocessor Communication Function
257
Interrupts
265
Table 14.6 SCI3 Interrupt Requests
265
Usage Notes
266
Section 15 I C Bus Interface 2 (IIC2)
269
Features
269
Figure 15.1 Block Diagram of I
270
Input/Output Pins
271
Table 15.1 Pin Configuration
271
Figure 15.2 External Circuit Connections of I/O Pins
271
Register Descriptions
272
- C Bus Control Register 1 (ICCR1)
  272
- Table 15.2 Transfer Rate
  274
- C Bus Control Register 2 (ICCR2)
  275
- C Bus Mode Register (ICMR)
  276
- C Bus Interrupt Enable Register (ICIER)
  278
- C Bus Status Register (ICSR)
  280
- Slave Address Register (SAR)
  282
- C Bus Transmit Data Register (ICDRT)
  283
- C Bus Receive Data Register (ICDRR)
  283
- C Bus Shift Register (ICDRS)
  283
Operation
284
Table 15.3 Interrupt Requests
300
Interrupts
300
Figure 15.21 Timing of Bit Synchronous Circuit
301
Table 15.4 Time for Monitoring SCL
301
Bit Synchronous Circuit
301
Usage Notes
302
- Issue (Retransmission) of Start/Stop Conditions
  302
- WAIT Setting in I C Bus Mode Register (ICMR)
  302
Section 16 A/D Converter
303
Features
303

Renesas H8/36912 Series User Manual (408 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 3.85 MB

General Precautions on Handling of Product
4
Preface
6
Table of Contents
9
Appendix
24
Section 1 Overview
29
Features
29
Internal Block Diagram
31
- Figure 1.1 Internal Block Diagram of H8/36912 Group
  31
  - Figure 1.2 Internal Block Diagram of H8/36902 Group
    32
  - Section 2 CPU
    32
- Section 2 CPU
  31
Figure 1.3 Pin Arrangement of H8/36912 Group (LQFP-32)
33
Pin Arrangement
33
Figure 1.4 Pin Arrangement of H8/36902 Group (LQFP-32)
34
Figure 1.5 Pin Arrangement of H8/36912 Group (SOP-32)
35
Figure 1.6 Pin Arrangement of H8/36902 Group (SOP-32)
36
Table 1.1 Pin Functions
37
Pin Functions
37
Manual
38
Section 2 CPU
39
Address Space and Memory Map
40
Figure 2.1 Memory Map (1)
40
Figure 2.1 Memory Map (2)
41
Register Configuration
42
Data Formats
46
Instruction Set
49
Addressing Modes and Effective Address Calculation
59
Basic Bus Cycle
64
Figure 2.11 CPU Operation States
66
Figure 2.12 State Transitions
66
CPU States
66
Usage Notes
67
Section 3 Exception Handling
73
Exception Sources and Vector Address
73
Register Descriptions
75
Reset Exception Handling
80
Interrupt Exception Handling
81
Usage Notes
86
Section 4 Address Break
87
Register Descriptions
87
Operation
91
Figure 4.2 Address Break Interrupt Operation Example (1)
91
Figure 4.2 Address Break Interrupt Operation Example (2)
92
Section 5 Clock Pulse Generators
93
Figure 5.1 Block Diagram of Clock Pulse Generators
93
Features
94
Register Descriptions
95
System Clock Select Operation
99
Figure 5.9 Example of Trimming Flow for Internal RC Oscillator Frequency
106
Trimming of Internal RC Oscillator Frequency
106
Figure 5.10 Timing Chart of Trimming of Internal RC Oscillator Frequency
107
External Oscillators
108
Prescaler
109
Usage Notes
110
- Note on Resonators
  110
- Notes on Board Design
  110
- Figure 5.15 Example of Incorrect Board Design
  110
Section 6 Power-Down Modes
111
Register Descriptions
112
Mode Transitions and States of LSI
117
Operating Frequency in Active Mode
120
Direct Transition
120
Module Standby Function
120
Section 7 ROM
121
Block Configuration
122
Figure 7.1 Flash Memory Block Configuration
123
Register Descriptions
124
On-Board Programming Modes
127
Flash Memory Programming/Erasing
131
Program/Erase Protection
136
- Hardware Protection
  136
- Software Protection
  136
- Error Protection
  136
Section 8 RAM
137
Section 9 I/O Ports
139
Port 1
139
- Figure 9.1 Port 1 Pin Configuration
  139
- Port Mode Register 1 (PMR1)
  140
- Port Control Register 1 (PCR1)
  141
- Port Data Register 1 (PDR1)
  141
- Pin Functions
  142
- Port Pull-Up Control Register 1 (PUCR1)
  142
Port 2
143
- Port Control Register 2 (PCR2)
  143
- Figure 9.2 Port 2 Pin Configuration
  143
- Port Data Register 2 (PDR2)
  144
- Pin Functions
  144
Port 5
145
- Figure 9.3 Port 5 Pin Configuration
  145
- Port Control Register 5 (PCR5)
  146
- Port Mode Register 5 (PMR5)
  146
- Port Data Register 5 (PDR5)
  147
- Port Pull-Up Control Register 5 (PUCR5)
  147
- Pin Functions
  148
Port 7
149
- Port Control Register 7 (PCR7)
  149
- Figure 9.4 Port 7 Pin Configuration
  149
- Port Data Register 7 (PDR7)
  150
- Pin Functions
  150
Port 8
151
- Figure 9.5 Port 8 Pin Configuration
  151
- Port Control Register 8 (PCR8)
  152
- Port Data Register 8 (PDR8)
  152
- Pin Functions
  153
Port B
155
- Port Data Register B (PDRB)
  155
- Figure 9.6 Port B Pin Configuration
  155
- Pin Functions
  156
Port C
158
- Figure 9.7 Port C Pin Configuration
  158
- Pin Functions
  159
- Port Control Register C (PCRC)
  159
- Port Data Register C (PDRC)
  159
Figure 10.1 Block Diagram of Timer B1
161
Section 10 Timer B1
161
Features
161
Register Descriptions
162
- Timer Mode Register B1 (TMB1)
  162
- Timer Counter B1 (TCB1)
  163
- Timer Load Register B1 (TLB1)
  163
Table 10.1 Timer B1 Operating Modes
164
Operation
164
- Interval Timer Operation
  164
- Auto-Reload Timer Operation
  164
Timer B1 Operating Modes
164
Section 11 Timer V
165
Features
165
Table 11.1 Pin Configuration
166
Input/Output Pins
166
Register Descriptions
167
Operation
172
Timer V Application Examples
175
Figure 11.11 Contention between TCNTV Write and Clear
177
Usage Notes
177
Figure 11.12 Contention between TCORA Write and Compare Match
178
Figure 11.13 Internal Clock Switching and TCNTV Operation
178
Section 12 Timer W
179
Features
179
Table 12.1 Timer W Functions
180
Figure 12.1 Timer W Block Diagram
181
Table 12.2 Pin Configuration
181
Input/Output Pins
181
Register Descriptions
182
- Timer Mode Register W (TMRW)
  183
- Timer Control Register W (TCRW)
  184
- Timer Interrupt Enable Register W (TIERW)
  185
- Timer Status Register W (TSRW)
  186
- Timer I/O Control Register 0 (TIOR0)
  188
- Timer I/O Control Register 1 (TIOR1)
  189
- Timer Counter (TCNT)
  191
- General Registers a to D (GRA to GRD)
  191
Operation
192
Operation Timing
200
Usage Notes
206
Figure 12.24 Contention between TCNT Write and Clear
207
Figure 12.25 Internal Clock Switching and TCNT Operation
207
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur
208
Figure 13.1 Block Diagram of Watchdog Timer
209
Section 13 Watchdog Timer
209
Features
209
Register Descriptions
210
Figure 13.2 Watchdog Timer Operation Example
213
Operation
213
Section 14 Serial Communication Interface 3 (SCI3)
215
Features
215
Figure 14.1 Block Diagram of SCI3
216
Input/Output Pins
217
Register Descriptions
217
Operation in Asynchronous Mode
230
Operation in Clocked Synchronous Mode
236
Multiprocessor Communication Function
243
Table 14.6 SCI3 Interrupt Requests
250
Interrupts
250
Usage Notes
251
Section 15 I C Bus Interface 2 (IIC2)
253
Features
253
Figure 15.1 Block Diagram of I
254
Input/Output Pins
255
Register Descriptions
255
- Figure 15.2 External Circuit Connections of I/O Pins
  255
- Table 15.1 Pin Configuration
  255
- C Bus Control Register 1 (ICCR1)
  256
- C Bus Control Register 2 (ICCR2)
  257
- Table 15.2 Transfer Rate
  257
- C Bus Mode Register (ICMR)
  259
- C Bus Interrupt Enable Register (ICIER)
  260
- C Bus Status Register (ICSR)
  262
- Slave Address Register (SAR)
  264
- C Bus Receive Data Register (ICDRR)
  265
- C Bus Shift Register (ICDRS)
  265
- C Bus Transmit Data Register (ICDRT)
  265
Operation
266
Table 15.3 Interrupt Requests
281
Interrupts
281
Figure 15.21 Timing of Bit Synchronous Circuit
282
Table 15.4 Time for Monitoring SCL
282
Bit Synchronous Circuit
282
Section 16 A/D Converter
283

Renesas H8/36912 Series User Manual (37 pages)

H8 Family / H8/300H Tiny Series System Interface Cable

Brand: Renesas | Category: Computer Hardware | Size: 0.38 MB

Important Information
7
Limited Warranty
8
Table of Contents
14
Section 1 Configuration

15
Section 2 Connection Procedures

17
Section 3 Installing the MCU to the User System

27
Section 4 Verifying Operation

29
Section 5 Notice

31

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Renesas H8/36912 Series Manuals

Renesas H8/36912 Series Hardware Manual (442 pages)

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Renesas H8/36912 Series User Manual (408 pages)

Table of Contents

Renesas H8/36912 Series User Manual (37 pages)

Table of Contents

Section 1 Configuration

Section 2 Connection Procedures

Section 3 Installing the MCU to the User System

Section 4 Verifying Operation

Section 5 Notice

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