Timing Of Status Flag Setting - Renesas H8/3067 Series User Manual

Section 10 8-Bit Timers
φ
Input capture input
Input capture signal
TCNT N
TCORB N
Figure 10.13 Timing of Input Capture Input Signal
10.4.4

Timing of Status Flag Setting

Timing of CMFA/CMFB Flag Setting when Compare Match Occurs: CMFA and CMFB in
TCSR are set to 1 by the compare match signal output when the TCOR and TCNT values match.
The compare match signal is generated in the last state of the match (when the matched TCNT
count value is updated). Therefore, after the TCNT and TCOR values match, the compare match
signal is not generated until an incrementing clock pulse is generated. Figure 10.14 shows the
timing in this case.
φ
TCNT N N+1
TCOR
N
Compare match signal
CMF
Figure 10.14 CMF Flag Setting Timing when Compare Match Occurs
Timing of CMFB Flag Setting when Input Capture Occurs: On generation of an input capture
signal, the CMFB flag is set to 1 and at the same time the TCNT value is transferred to TCORB.
Figure 10.15 shows the timing in this case.
Rev. 4.00 Jan 26, 2006 page 418 of 938
REJ09B0276-0400