Figure 17.24 Stop Condition Issuance Timing; Figure 17.25 Iric Flag Clearing Timing When Wait = 1 - Renesas H8S/2158 User Manual

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Section 17 I C Bus Interface (IIC)
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9. Note on when I C bus interface stop condition instruction is issued
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low, as shown in figure 17.24.
SCL
SDA
IRIC
10. Note on IRIC flag clearing when wait function is used
When the wait function is used in I
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL pin is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
SCL
SDA
IRIC

Figure 17.25 IRIC Flag Clearing Timing When WAIT = 1

Rev. 3.00 Jan 25, 2006 page 546 of 872
REJ09B0286-0300
Secures a high period
9th clock
V
IH
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low judgement

Figure 17.24 Stop Condition Issuance Timing

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C bus interface master mode and in a situation where the
Secures a high period
9th clock
V
IH
SCL = low detected
[1] SCL = low determination
Stop condition generation
[2] Stop condition instruction issuance
[2] IRIC clear