Figure 12.44 Tciu Interrupt Setting Timing; Figure 12.45 Timing For Status Flag Clearing By Cpu - Renesas H8S/2437 Hardware Manual

φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
TCIU interrupt
Status Flag Clearing Timing:
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 12.45 shows the
timing for status flag clearing by the CPU.
Address
Write signal
Status flag
Interrupt
request
signal

Figure 12.45 Timing for Status Flag Clearing by CPU

Rev. 1.00, 09/03, page 356 of 704
H'0000

Figure 12.44 TCIU Interrupt Setting Timing

TSR write cycle
H'FFFF
T T
1 2
TSR address