Figure 10.41 Tciu Interrupt Setting Timing; Figure 10.42 Timing For Status Flag Clearing By Cpu - Renesas H8S/2368 Series Hardware Manual

φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
TCIU interrupt
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10.42
shows the timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status
flag clearing by the DTC or DMAC*.
Note: * Not supported by the H8S/2366.
φ
Address
Write signal
Status flag
Interrupt
request
signal

Figure 10.42 Timing for Status Flag Clearing by CPU

H'0000

Figure 10.41 TCIU Interrupt Setting Timing

H'FFFF
TSR write cycle
T T
1 2
TSR address
Rev. 2.00, 05/03, page 443 of 820