Renesas SH7709S 32-bit Microcontrollers Manuals

Manuals and User Guides for Renesas SH7709S 32-bit Microcontrollers. We have 1 Renesas SH7709S 32-bit Microcontrollers manual available for free PDF download: Hardware Manual

Renesas SH7709S Hardware Manual (807 pages)

32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series

Brand: Renesas | Category: Computer Hardware | Size: 4.61 MB

Table of Contents
17
Section 1 Overview and Pin Functions

45
- SH7709S Features
  45
Tables

46
- Table 1.1 SH7709S Features
  46
- Table 1.2 Characteristics
  49
- Block Diagram
  50
- Figure 1.1 Block Diagram
  50
- Figures
  
  50
- Pin Description
  51
Section 2 CPU

63
Section 3 Memory Management Unit (MMU)

99
- Overview
  99
  - Features
    99
  - Role of MMU
    99
  - Figure 3.1 MMU Functions
    101
  - Sh7709S Mmu
    102
  - Figure 3.2 Virtual Address Space Mapping
    103
  - Register Configuration
    105
- Register Description
  105
- Table 3.1 Register Configuration
  105
- Figure 3.3 MMU Register Contents
  106
- TLB Functions
  107
- MMU Functions
  113
  - MMU Hardware Management
    113
  - MMU Software Management
    113
  - MMU Instruction (LDTLB)
    114
  - Figure 3.9 Operation of LDTLB Instruction
    115
  - Avoiding Synonym Problems
    116
  - Figure 3.10 Synonym Problem
    117
- MMU Exceptions
  118
- Configuration of Memory-Mapped TLB
  124
  - Address Array
    124
  - Figure 3.13 MMU Exception Signals in Data Access
    124
  - Data Array
    125
  - Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access
    126
  - Usage Examples
    127
- Usage Note
  127
Section 4 Exception Handling

129
- Overview
  129
  - Features
    129
  - Register Configuration
    129
- Exception Handling Function
  129
  - Exception Handling Flow
    129
  - Table 4.1 Register Configuration
    129
  - Exception Vector Addresses
    130
  - Figure 4.1 Vector Table
    130
  - Table 4.2 Exception Event Vectors
    131
  - Acceptance of Exceptions
    132
  - Figure 4.2 Example of Acceptance Order of General Exceptions
    133
  - Exception Codes
    134
  - Table 4.3 Exception Codes
    134
  - Exception Request Masks
    135
  - Returning from Exception Handling
    135
- Register Descriptions
  136
- Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers
  136
- Exception Handling Operation
  137
  - Reset
    137
  - Interrupts
    137
  - General Exceptions
    138
- Individual Exception Operations
  138
  - Resets
    138
  - General Exceptions
    139
  - Table 4.4 Types of Reset
    139
  - Interrupts
    143
- Cautions
  144
Section 5 Cache

147
- Overview
  147
  - Features
    147
  - Cache Structure
    147
  - Table 5.1 Cache Specifications
    147
  - Figure 5.1 Cache Structure
    148
  - Register Configuration
    149
- Register Description
  149
- Cache Operation
  153
  - Searching the Cache
    153
  - Figure 5.4 Cache Search Scheme (Normal Mode)
    154
  - Read Access
    155
  - Prefetch Operation
    155
  - Write Access
    155
  - Write-Back Buffer
    155
  - Coherency of Cache and External Memory
    156
- Memory-Mapped Cache
  156
  - Address Array
    156
  - Figure 5.5 Write-Back Buffer Configuration
    156
  - Data Array
    157
  - Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
    158
  - Examples of Usage
    159
Section 6 Interrupt Controller (INTC)

161
- Overview
  161
  - Features
    161
  - Block Diagram
    162
  - Figure 6.1 Block Diagram of INTC
    162
  - Pin Configuration
    163
  - Table 6.1 INTC Pins
    163
  - Register Configuration
    164
  - Table 6.2 INTC Registers
    164
- Interrupt Sources
  165
- INTC Registers
  175
- INTC Operation
  187
  - Interrupt Sequence
    187
  - Figure 6.3 Interrupt Operation Flowchart
    188
  - Multiple Interrupts
    189
- Interrupt Response Time
  189
- Table 6.8 Interrupt Response Time
  190
- Figure 6.4 Example of Pipeline Operations When IRL Interrupt Is Accepted
  192
Section 7 User Break Controller

193
- Overview
  193
  - Features
    193
  - Block Diagram
    194
  - Figure 7.1 Block Diagram of User Break Controller
    194
  - Register Configuration
    195
  - Table 7.1 Register Configuration
    195
- Register Descriptions
  196
  - Break Address Register a (BARA)
    196
  - Break Address Mask Register a (BAMRA)
    197
  - Break Bus Cycle Register a (BBRA)
    198
  - Break Address Register B (BARB)
    200
  - Break Address Mask Register B (BAMRB)
    201
  - Break Data Register B (BDRB)
    202
  - Break Data Mask Register B (BDMRB)
    203
  - Break Bus Cycle Register B (BBRB)
    204
  - Break Control Register (BRCR)
    206
  - Execution Times Break Register (BETR)
    210
  - Branch Source Register (BRSR)
    211
  - Branch Destination Register (BRDR)
    212
  - Break ASID Register a (BASRA)
    213
  - Break ASID Register B (BASRB)
    213
- Operation Description
  214
  - Flow of the User Break Operation
    214
  - Break on Instruction Fetch Cycle
    214
  - Break by Data Access Cycle
    215
  - Table 7.2 Data Access Cycle Addresses and Operand Size Comparison Conditions
    215
  - Sequential Break
    216
  - Value of Saved Program Counter
    216
  - PC Trace
    217
  - Usage Examples
    218
  - Notes
    223
Section 8 Power-Down Modes

225
- Overview
  225
  - Power-Down Modes
    225
  - Table 8.1 Power-Down Modes
    226
  - Pin Configuration
    227
  - Register Configuration
    227
- Register Descriptions
  227
- Sleep Mode
  231
  - Transition to Sleep Mode
    231
  - Canceling Sleep Mode
    231
  - Precautions When Using the Sleep Mode
    231
- Standby Mode
  232
  - Transition to Standby Mode
    232
  - Table 8.4 Register States in Standby Mode
    232
  - Canceling Standby Mode
    233
  - Figure 8.1 Canceling Standby Mode with STBCR.STBY
    233
  - Clock Pause Function
    234
- Module Standby Function
  235
  - Transition to Module Standby Function
    235
  - Clearing Module Standby Function
    235
- Timing of STATUS Pin Changes
  236
- Hardware Standby Mode
  243
Section 9 On-Chip Oscillation Circuits

247
- Overview
  247
  - Features
    247
- Overview of CPG
  248
  - CPG Block Diagram
    248
  - Figure 9.1 Block Diagram of Clock Pulse Generator
    248
  - CPG Pin Configuration
    250
  - CPG Register Configuration
    250
  - Table 9.1 CPG Pins and Functions
    250
  - Table 9.2 CPG Register
    250
- Clock Operating Modes
  251
- Table 9.3 Clock Operating Modes
  251
- Table 9.4 Available Combinations of Clock Mode and FRQCR Values
  252
- Register Descriptions
  255
  - Frequency Control Register (FRQCR)
    255
- Changing the Frequency
  257
  - Changing the Multiplication Rate
    257
  - Changing the Division Ratio
    257
- Overview of WDT
  258
  - Block Diagram of WDT
    258
  - Register Configuration
    258
  - Figure 9.2 Block Diagram of WDT
    258
  - Table 9.5 Register Configuration
    258
- WDT Registers
  259
- Using the WDT
  262
  - Canceling Standby
    262
  - Changing the Frequency
    262
  - Using Watchdog Timer Mode
    263
  - Using Interval Timer Mode
    263
- Notes on Board Design
  264
- Figure 9.4 Points for Attention When Using Crystal Resonator
  264
- Figure 9.5 Points for Attention When Using PLL Oscillator Circuit
  265
Section 10 Bus State Controller (BSC)

267
Section 11 Direct Memory Access Controller (DMAC)

371
Section 12 Timer (TMU)

433
- Overview
  433
  - Features
    433
  - Block Diagram
    434
  - Figure 12.1 Block Diagram of TMU
    434
  - Pin Configuration
    435
  - Register Configuration
    435
  - Table 12.1 TMU Pin
    435
  - Table 12.2 TMU Registers
    435
- TMU Registers
  436
  - Timer Output Control Register (TOCR)
    436
  - Timer Start Register (TSTR)
    436
  - Timer Control Registers (TCR)
    437
  - Timer Constant Registers (TCOR)
    441
  - Timer Counters (TCNT)
    441
  - Input Capture Register (TCPR2)
    443
- TMU Operation
  444
- Interrupts
  448
- Usage Notes
  450
  - Writing to Registers
    450
  - Reading Registers
    450
Section 13 Realtime Clock (RTC)

451
- Overview
  451
  - Features
    451
  - Block Diagram
    452
  - Figure 13.1 Block Diagram of RTC
    452
  - Pin Configuration
    453
  - Table 13.1 RTC Pins
    453
  - RTC Register Configuration
    454
  - Table 13.2 RTC Registers
    454
- RTC Registers
  455
  - 64-Hz Counter (R64CNT)
    455
  - Second Counter (RSECCNT)
    455
  - Minute Counter (RMINCNT)
    456
  - Hour Counter (RHRCNT)
    456
  - Day of Week Counter (RWKCNT)
    457
  - Table 13.3 Day-Of-Week Codes (RWKCNT)
    457
  - Date Counter (RDAYCNT)
    458
  - Month Counter (RMONCNT)
    458
  - Year Counter (RYRCNT)
    459
  - Second Alarm Register (RSECAR)
    459
  - Minute Alarm Register (RMINAR)
    460
  - Hour Alarm Register (RHRAR)
    460
  - Day of Week Alarm Register (RWKAR)
    461
  - Table 13.4 Day-Of-Week Codes (RWKAR)
    461
  - Date Alarm Register (RDAYAR)
    462
  - Month Alarm Register (RMONAR)
    462
  - RTC Control Register 1 (RCR1)
    463
  - RTC Control Register 2 (RCR2)
    464
- RTC Operation
  466
- Usage Notes
  470
Section 14 Serial Communication Interface (SCI)

471
Section 15 Smart Card Interface

533
Section 16 Serial Communication Interface with FIFO (SCIF)

555
Section 17 Irda

599
- Overview
  599
  - Features
    599
  - Block Diagram
    600
  - Figure 17.1 Block Diagram of Irda
    600
  - Figure 17.2 SCPT[3]/SCK1 Pin
    601
  - Figure 17.3 Scpt[2]/Txd1 Pin
    602
  - Pin Configuration
    603
  - Figure 17.4 Scpt[2]/Rxd1 Pin
    603
  - Table 17.1 Irda Pins
    603
  - Register Configuration
    604
  - Table 17.2 Irda Registers
    604
- Register Description
  605
  - Serial Mode Register (SCSMR)
    605
- Operation Description
  607
  - Overview
    607
  - Transmitting
    607
  - Receiving
    608
  - Figure 17.5 Transmit/Receive Operation
    608
Section 18 Pin Function Controller

609
- Overview
  609
- Table 18.1 List of Multiplexed Pins
  609
- Register Configuration
  613
- Table 18.2 Pin Function Controller Registers
  613
- Register Descriptions
  614
  - Port a Control Register (PACR)
    614
  - Port B Control Register (PBCR)
    615
  - Port C Control Register (PCCR)
    616
  - Port D Control Register (PDCR)
    617
  - Port E Control Register (PECR)
    618
  - Port F Control Register (PFCR)
    619
  - Port G Control Register
    620
  - Port H Control Register (PHCR)
    621
  - Port J Control Register (PJCR)
    623
  - Port K Control Register (PKCR)
    624
  - Port L Control Register (PLCR)
    625
  - SC Port Control Register (SCPCR)
    626
Section 19 I/O Ports

631
- Overview
  631
- Port a
  631
  - Register Description
    631
  - Figure 19.1 Port a
    631
  - Table 19.1 Port a Register
    631
  - Port a Data Register (PADR)
    632
  - Table 19.2 Port a Data Register (PADR) Read/Write Operations
    632
- Port B
  633
  - Register Description
    633
  - Figure 19.2 Port B
    633
  - Table 19.3 Port B Register
    633
  - Port B Data Register (PBDR)
    634
  - Table 19.4 Port B Data Register (PBDR) Read/Write Operations
    634
- Port C
  635
  - Register Description
    635
  - Figure 19.3 Port C
    635
  - Table 19.5 Port C Register
    635
  - Port C Data Register (PCDR)
    636
  - Table 19.6 Port C Data Register (PCDR) Read/Write Operations
    636
- Port D
  637
  - Register Description
    637
  - Figure 19.4 Port D
    637
  - Table 19.7 Port D Register
    637
  - Port D Data Register (PDDR)
    638
  - Table 19.8 Port D Data Register (PDDR) Read/Write Operations
    638
- Port E
  639
  - Register Description
    639
  - Figure 19.5 Port E
    639
  - Table 19.9 Port E Register
    639
  - Port E Data Register (PEDR)
    640
  - Table 19.10 Port E Data Register (PEDR) Read/Write Operations
    640
- Port F
  641
  - Register Description
    641
  - Figure 19.6 Port F
    641
  - Table 19.11 Port F Register
    641
  - Port F Data Register (PFDR)
    642
  - Table 19.12 Port F Data Register (PFDR) Read/Write Operations
    642
- Port G
  643
  - Register Description
    643
  - Figure 19.7 Port G
    643
  - Table 19.13 Port G Register
    643
  - Port G Data Register
    644
  - Table 19.14 Port G Data Register (PGDR) Read/Write Operations
    644
- Port H
  645
  - Register Description
    645
  - Figure 19.8 Port H
    645
  - Table 19.15 Port H Register
    645
  - Port H Data Register (PHDR)
    646
  - Table 19.16 Port H Data Register (PHDR) Read/Write Operations
    646
- Port J
  647
- Port K
  649
- Port L
  651
- SC Port
  653
Section 20 A/D Converter

657
Section 21 D/A Converter

679
- Overview
  679
  - Features
    679
  - Block Diagram
    679
  - Figure 21.1 Block Diagram of D/A Converter
    679
  - I/O Pins
    680
  - Register Configuration
    680
  - Table 21.1 D/A Converter Pins
    680
  - Table 21.2 D/A Converter Registers
    680
- Register Descriptions
  681
  - D/A Data Registers 0 and 1 (DADR0/1)
    681
  - D/A Control Register (DACR)
    681
- Operation
  683
- Figure 21.2 Example of D/A Converter Operation
  683
Section 22 User Debugging Interface (UDI)

685
- Overview
  685
- User Debugging Interface (UDI)
  685
  - Pin Descriptions
    685
  - Block Diagram
    686
- Register Descriptions
  686
  - Figure 22.1 Block Diagram of UDI
    686
  - Bypass Register (SDBPR)
    687
  - Instruction Register (SDIR)
    687
  - Table 22.1 UDI Registers
    687
  - Boundary Scan Register (SDBSR)
    688
  - Table 22.2 UDI Commands
    688
  - Table 22.3 Pins of this LSI and Boundary Scan Register Bits
    689
- UDI Operation
  695
  - TAP Controller
    695
  - Figure 22.2 TAP Controller State Transitions
    695
  - Reset Configuration
    696
  - Table 22.4 Reset Configuration
    696
  - UDI Reset
    697
  - UDI Interrupt
    697
  - Bypass
    697
  - Using UDI to Recover from Sleep Mode
    697
  - Figure 22.3 UDI Reset
    697
- Boundary Scan
  698
  - Supported Instructions
    698
  - Points for Attention
    699
- Usage Notes
  699
- Advanced User Debugger (AUD)
  699
Section 23 Electrical Characteristics

701
Appendix A Pin Functions

759
Appendix B Memory-Mapped Control Registers

783
- Register Address Map
  783
- Table B.1 Memory-Mapped Control Registers
  783
- Register Bits
  789
- Table B.2 Register Bits
  789
Appendix C Product Lineup

801
- Table C.1 SH7709S Models
  801
Appendix D Package Dimensions

802

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Renesas SH7709S Hardware Manual (807 pages)

Table of Contents

Section 1 Overview and Pin Functions

Tables

Figures

Section 2 CPU

Section 3 Memory Management Unit (MMU)

Section 4 Exception Handling

Section 5 Cache

Section 6 Interrupt Controller (INTC)

Section 7 User Break Controller

Section 8 Power-Down Modes

Section 9 On-Chip Oscillation Circuits

Section 10 Bus State Controller (BSC)

Section 11 Direct Memory Access Controller (DMAC)

Section 12 Timer (TMU)

Section 13 Realtime Clock (RTC)

Section 14 Serial Communication Interface (SCI)

Section 15 Smart Card Interface

Section 16 Serial Communication Interface with FIFO (SCIF)

Section 17 Irda

Section 18 Pin Function Controller

Section 19 I/O Ports

Section 20 A/D Converter

Section 21 D/A Converter

Section 22 User Debugging Interface (UDI)

Section 23 Electrical Characteristics

Appendix A Pin Functions

Appendix B Memory-Mapped Control Registers

Appendix C Product Lineup

Appendix D Package Dimensions

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