Figure 9.43 Timing For Status Flag Clearing By Cpu; Figure 9.44 Timing For Status Flag Clearing By Dmac Activation (1) - Renesas H8SX/1520 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figure 9.43 shows the timing for status flag clearing by
the CPU, and figure 9.44 shows the timing for status flag clearing by the DMAC.
Pφ
Address
Write
Status flag
Interrupt request
signal
The status flag and interrupt request signal are cleared in synchronization with Pφ after the DMAC
transfer has started, as shown in figure 9.44. If conflict occurs for clearing the status flag and
interrupt request signal due to activation of multiple DMAC transfers, it will take up to five clock
cycles (Pφ) for clearing them, as shown in figure 9.45. The next transfer request is masked for a
longer period of either a period until the current transfer ends or a period for five clock cycles (Pφ)
from the beginning of the transfer.
Pφ
Address
Status flag
Interrupt request
signal

Figure 9.44 Timing for Status Flag Clearing by DMAC Activation (1)

Rev. 3.00 Mar. 14, 2006 Page 336 of 804
REJ09B0104-0300
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Figure 9.43 Timing for Status Flag Clearing by CPU

Period in which the next transfer request is masked
TSR write cycle
T1 T2
TSR address
DMAC DMAC
read cycle write cycle
T1 T2 T1 T2
Source Destination
address address