Figure 10.41 Tciu Interrupt Setting Timing; Figure 10.42 Timing For Status Flag Clearing By Cpu - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)
φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
TCIU interrupt
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the
timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag
clearing by the DTC.
φ
Address
Write signal
Status flag
Interrupt
request
signal

Figure 10.42 Timing for Status Flag Clearing by CPU

Rev. 6.00 Mar 15, 2006 page 232 of 570
REJ09B0211-0600
H'0000

Figure 10.41 TCIU Interrupt Setting Timing

TSR write cycle
H'FFFF
T T
1 2
TSR address