Interrupt Exception Handling Sequence - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer
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Section 6 Interrupt Controller
6.6.3

Interrupt Exception Handling Sequence

Figure 6.10 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Figure 6.10 Interrupt Exception Handling
Rev. 1.00 May 09, 2008 Page 138 of 954
REJ09B0462-0100

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