Interrupt Exception Handling Sequence; Figure 5.5 Interrupt Exception Handling - Renesas H8SX/1520 Series Hardware Manual

32-bit cisc microcomputer

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Section 5 Interrupt Controller

Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where

interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on-

chip memory.

Rev. 3.00 Mar. 14, 2006 Page 116 of 804

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