Interrupt Exception Handling Sequence; Figure 5.7 Interrupt Exception Handling - Renesas H8S/2111B Hardware Manual

Bit single-chip microcomputer h8s family / h8s/2100 series
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5.6.3

Interrupt Exception Handling Sequence

Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.

Figure 5.7 Interrupt Exception Handling

Rev. 1.00, 05/04, page 85 of 544

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