Interrupt Exception Handling Sequence - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Section 5 Interrupt Controller
5.6.3

Interrupt Exception Handling Sequence

Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where
interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on-
chip memory.
Figure 5.5 Interrupt Exception Handling
Rev.2.00 Jun. 28, 2007 Page 110 of 666
REJ09B0311-0200

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