Input/Output Pins; Figure 5.1 Block Diagram Of Interrupt Controller; Table 5.1 Pin Configuration - Renesas H8S/2111B Hardware Manual

SYSCR
NMI input
IRQ input
KIN input
WUE input
Internal
interrupt request
WOVI0 to IBFI3
[Legend]
Interrupt control register
ICR:
IRQ sense control register
ISCR:
IRQ enable register
IER:
IRQ status register
ISR:
5.2

Input/Output Pins

Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Symbol
NMI
IRQ7 to IRQ0
KIN15 to KIN0
WUE7 to WUE0
Rev. 1.00, 05/04, page 68 of 544
INTM1, INTM0
NMIEG
NMI input
IRQ input
ISR
ISCR IER
KMIMR
WUEMR
KIN and WUE
input
Interrupt controller
KMIMR:
WUEMR:
SYSCR:

Figure 5.1 Block Diagram of Interrupt Controller

I/O Function
Input Nonmaskable external interrupt
Rising edge or falling edge can be selected
Input Maskable external interrupts
Rising edge, falling edge, both edges, or level sensing,
can be selected individually for each pin.
Input Maskable external interrupts
Falling edge or level sensing can be selected.
Input Maskable external interrupts
Falling edge or level sensing can be selected.
Priority check
ICR
Keyboard matrix interrupt mask register
Wake-up event interrupt mask register
System control register
CPU
Interrupt
request
Vector number
I, UI
CCR