Figure 11.1 Block Diagram Of User Break Controller - Renesas HD6417641 Hardware Manual

Section 11 User Break Controller (UBC)
Figure 11.1 shows a block diagram of the UBC.
Access
ASID
Control
LDB/IDB/
XDB/YDB
[Legend]
BBRA:
BARA:
BAMRA:
BASRA:
BBRB:
BARB:
BAMRB:

Figure 11.1 Block Diagram of User Break Controller

Rev. 4.00 Sep. 14, 2005 Page 242 of 982
REJ09B0023-0400
XAB/YAB
IAB LAB
CPU state
signals
Break bus cycle register A
Break address register A
Break address mask register A
Break ASID register A
Break bus cycle register B
Break address register B
Break address mask register B
Access
BBRA
comparator
BARA
Address
comparator
BAMRA
ASID
BASRA
comparator
Channel A
Access
BBRB
comparator
BARB
Address
comparator
BAMRB
ASID
BASRB
comparator
BBRB
Data
comparator
BDMRB
Channel B
BETR
BRSR
PC trace
BRDR
CONTROL BRCR
User break request
UBC Location
BASRB: Break ASID register B
BDRB: Break data register B
BDMRB: Break data mask register B
BETR: Break execution times register
BRSR: Branch source register
BRDR: Branch destination register
BRCR: Break control register
Internal bus
CCN Location