Input/Output Pins; Figure 5.1 Block Diagram Of Interrupt Controller - Renesas H8SX/1520 Series Hardware Manual

Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
NMI input
IRQ input
Internal interrupt sources
WOVI to SSTXI2
5.2

Input/Output Pins

Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1 Pin Configuration
Name
NMI
IRQ14 to IRQ0
Rev. 3.00 Mar. 14, 2006 Page 88 of 804
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INTM1, INTM0
INTCR
NMIEG
NMI input unit
IRQ input unit
ISCR IER
Source selecter
Interrupt controller
[Legend]
INTCR: Interrupt control register
CPU priority control register
CPUPCR:
IRQ sense control register
ISCR:
IER: IRQ enable register

Figure 5.1 Block Diagram of Interrupt Controller

I/O Function
Input Nonmaskable External Interrupt
Rising or falling edge can be selected.
Input Maskable External Interrupts
Rising, falling, or both edges, or level sensing, can be selected.
IPR
ISR
Priority
decision unit
SSIER
CPUPCR
ISR: IRQ status register
Software standby release IRQ enable register
SSIER:
Interrupt priority register
IPR:
CPU
I
CCR
I2 to I0
EXR
CPU
interrupt request
CPU
vector
DMAC
DMAC
activation
DMAC priority
enable
control
DMDR