Renesas SH7763 32-bit Microcontrollers Manuals

Manuals and User Guides for Renesas SH7763 32-bit Microcontrollers. We have 1 Renesas SH7763 32-bit Microcontrollers manual available for free PDF download: Hardware Manual

Renesas SH7763 Hardware Manual (2026 pages)

Renesas 32-Bit RISC Microcomputer SuperH RISC Engine Family SH-4A Series

Brand: Renesas | Category: Computer Hardware | Size: 11.98 MB

Table of Contents
9
Section 1 Overview
67
Features of the SH7763
67
Section 1 Overview
68
Figure 1.1 SH7763 Block Diagram
79
Block Diagram
79
Pin Arrangement
80
Figure 1.2 Pin Arrangement
81
Table 1.2 Pin Configuration
82
Section 2 Programming Model

103
- Data Formats
  103
- Figure 2.1 Data Formats
  103
- Register Descriptions
  104
  - Privileged Mode and Banks
    104
  - Table 2.1 Initial Register Values
    106
  - Figure 2.2 CPU Register Configuration in each Processing Mode
    107
  - General Registers
    108
  - Figure 2.3 General Registers
    108
  - Floating-Point Registers
    109
  - Figure 2.4 Floating-Point Registers
    110
  - Control Registers
    111
  - System Registers
    113
  - Figure 2.5 Relationship between SZ Bit and Endian
    116
  - Table 2.2 Bit Allocation for FPU Exception Handling
    116
- Memory-Mapped Registers
  117
- Data Formats in Registers
  118
- Data Formats in Memory
  118
- Figure 2.6 Formats of Byte Data and Word Data in Register
  118
- Processing States
  119
- Figure 2.7 Data Formats in Memory
  119
- Figure 2.8 Processing State Transitions
  120
- Usage Note
  121
  - Notes on Self-Modified Codes
    121
Section 3 Instruction Set

123
Section 4 Pipelining

145
Section 5 Exception Handling

171
- Summary of Exception Handling
  171
- Register Descriptions
  171
- Exception Handling Functions
  175
  - Exception Handling Flow
    175
  - Exception Handling Vector Addresses
    175
- Exception Types and Priorities
  176
- Exception Flow
  178
- Description of Exceptions
  182
  - Resets
    182
  - General Exceptions
    184
  - Interrupts
    198
  - Priority Order with Multiple Exceptions
    199
- Usage Notes
  201
Section 6 Memory Management Unit (MMU)

203
- Overview of MMU
  203
  - Figure 6.1 Role of MMU
    205
  - Address Spaces
    206
  - Figure 6.2 Virtual Address Space (at in MMUCR = 0)
    206
  - Figure 6.3 Virtual Address Space (at in MMUCR = 1)
    207
  - Figure 6.4 P4 Area
    209
  - Figure 6.5 Physical Address Space
    210
- Register Descriptions
  212
- TLB Functions
  222
- MMU Functions
  228
  - MMU Hardware Management
    228
  - MMU Software Management
    228
  - MMU Instruction (LDTLB)
    229
  - Hardware ITLB Miss Handling
    230
  - Figure 6.11 Operation of LDTLB Instruction
    230
  - Avoiding Synonym Problems
    231
- MMU Exceptions
  232
- Memory-Mapped TLB Configuration
  238
  - ITLB Address Array
    239
  - Figure 6.12 Memory-Mapped ITLB Address Array
    239
  - ITLB Data Array
    240
  - Figure 6.13 Memory-Mapped ITLB Data Array
    240
  - UTLB Address Array
    241
  - UTLB Data Array
    242
  - Figure 6.14 Memory-Mapped UTLB Address Array
    242
- 32-Bit Address Extended Mode
  243
- Usage Notes
  252
Section 7 Caches

253
- Features
  253
- Figure 7.1 Configuration of Operand Cache (OC)
  254
- Figure 7.2 Configuration of Instruction Cache (IC)
  255
- Register Descriptions
  256
- Operand Cache Operation
  263
  - Read Operation
    263
  - Prefetch Operation
    264
  - Write Operation
    265
  - Write-Back Buffer
    267
  - Write-Through Buffer
    267
  - OC Two-Way Mode
    267
  - Figure 7.3 Configuration of Write-Back Buffer
    267
  - Figure 7.4 Configuration of Write-Through Buffer
    267
- Instruction Cache Operation
  268
  - Read Operation
    268
  - Prefetch Operation
    269
  - IC Two-Way Mode
    269
- Cache Operation Instruction
  270
  - Coherency between Cache and External Memory
    270
  - Prefetch Operation
    271
- Memory-Mapped Cache Configuration
  272
  - IC Address Array
    272
  - Figure 7.5 Memory-Mapped IC Address Array
    273
  - IC Data Array
    274
  - Figure 7.6 Memory-Mapped IC Data Array
    274
  - OC Address Array
    275
  - OC Data Array
    276
  - Figure 7.7 Memory-Mapped OC Address Array
    276
  - Figure 7.8 Memory-Mapped OC Data Array
    277
- Store Queues
  278
  - SQ Configuration
    278
  - Writing to SQ
    278
  - Figure 7.9 Store Queue Configuration
    278
  - Transfer to External Memory
    279
  - Determination of SQ Access Exception
    280
  - Reading from SQ
    280
- Notes on Using 32-Bit Address Extended Mode
  281
Section 8 L Memory

283
- Features
  283
- Register Descriptions
  284
- Operation
  295
  - Access from the CPU and FPU
    295
  - Access from the Superhyway Bus Master Module
    295
  - Block Transfer
    295
- L Memory Protective Functions
  297
- Table 8.4 Protective Function Exceptions to Access L Memory
  297
- Usage Notes
  298
  - Page Conflict
    298
  - L Memory Coherency
    298
  - Sleep Mode
    298
- Note on Using 32-Bit Address Extended Mode
  298
Section 9 Interrupt Controller (INTC)

299
Section 10 Superhyway Bus Bridge (SBR)

379
- Features
  379
- Figure 10.1 SBR Block Diagram
  379
- Register Descriptions
  380
- Operation
  383
  - Superhyway Bus Interface
    383
  - Bus Arbitration
    383
  - Figure 10.2 Bus Arbitration by the SBR
    383
Section 11 Local Bus State Controller (LBSC)

385
Section 12 DDR-SDRAM Interface (DDRIF)

475
Section 13 PCI Controller (PCIC)

515
Section 14 Direct Memory Access Controller (DMAC)

631
Section 15 External CPU Interface (EXCPU)

687
Section 16 Clock Pulse Generator (CPG)

699
- Features
  699
- Figure 16.1 Block Diagram of CPG
  700
- Input/Output Pins
  702
- Table 16.1 Pin Configuration and Functions of CPG
  702
- Clock Operating Mode
  703
- Table 16.2 Clock Operating Modes
  703
- Register Descriptions
  704
- Notes on Board Design
  708
- Figure 16.2 Notes on Using Crystal Resonator
  708
- Figure 16.3 Notes on Using PLL or DLL Oscillator Circuit
  709
Section 17 Watchdog Timer and Reset (WDT)

711
Section 18 Power-Down Mode

733
Section 19 Timer Unit (TMU)

753
- Features
  753
- Figure 19.1 Block Diagram of TMU
  754
- Input/Output Pins
  755
- Table 19.1 Pin Configuration
  755
- Register Descriptions
  756
- Operation
  765
- Interrupts
  770
- Table 19.4 TMU Interrupt Sources
  770
- Usage Notes
  771
  - Register Writes
    771
  - Reading from TCNT
    771
  - External Clock Frequency
    771
Section 20 16-Bit Timer Pulse Unit (TPU)

773
Section 21 Compare Match Timer (CMT)

813
Section 22 Realtime Clock (RTC)

825
- Features
  825
  - Block Diagram
    826
  - Figure 22.1 Block Diagram of RTC
    826
- Input/Output Pins
  827
- Table 22.1 RTC Pins
  827
- Register Descriptions
  828
- Table 22.2 Register Configuration
  828
- Table 22.3 Register State in each Operating Mode
  829
- Register Descriptions
  830
  - 64 Hz Counter (R64CNT)
    830
  - Second Counter (RSECCNT)
    830
  - Minute Counter (RMINCNT)
    831
  - Hour Counter (RHRCNT)
    831
  - Day-Of-Week Counter (RWKCNT)
    832
  - Day Counter (RDAYCNT)
    833
  - Month Counter (RMONCNT)
    834
  - Year Counter (RYRCNT)
    834
  - Second Alarm Register (RSECAR)
    835
  - Minute Alarm Register (RMINAR)
    835
  - Hour Alarm Register (RHRAR)
    836
  - Day-Of-Week Alarm Register (RWKAR)
    836
  - Day Alarm Register (RDAYAR)
    837
  - Month Alarm Register (RMONAR)
    838
  - RTC Control Register 1 (RCR1)
    838
  - RTC Control Register 2 (RCR2)
    840
  - RTC Control Register (RCR3) and Year-Alarm Register (RYRAR)
    843
- Operation
  844
- Interrupts
  847
- Usage Notes
  847
Section 23 Gigabit Ethernet Controller (GETHER)

849
Section 24 IP Security Accelerator (SECURITY)

1061
Section 25 Stream Interface (STIF)

1063
Section 26 I C Bus Interface (IIC)

1091
- Features
  1091
- Figure 26.1 Block Diagram for I
  1091
- Input/Output Pins
  1092
- Register Descriptions
  1092
  - Table 26.1 Pin Configuration
    1092
  - Table 26.2 Register Configuration
    1092
  - Table 26.3 Register State in each Operating Mode
    1094
  - Slave Control Register (ICSCR)
    1095
  - Slave Status Register (ICSSR)
    1097
  - Slave Interrupt Enable Register (ICSIER)
    1100
  - Slave Address Register (ICSAR)
    1101
  - Master Control Register (ICMCR)
    1102
  - Master Status Register (ICMSR)
    1104
  - Master Interrupt Enable Register (ICMIER)
    1106
  - Clock Control Register (ICCCR)
    1107
  - Master Address Register (ICMAR)
    1107
  - Receive and Transmit Data Registers (ICRXD and ICTXD)
    1109
  - Table 26.4 Suggested Settings for CDF and SCGD
    1109
- Operations
  1110
  - Data and Clock Filters
    1110
  - Clock Generator
    1110
  - Master/Slave Interfaces
    1110
  - Software Status Interlocking
    1110
  - C Bus Data Format
    1112
  - Figure 26.2 I C Bus Timing
    1112
  - Table 26.5 Description on Symbols of I C Bus Data Format
    1112
  - 7-Bit Address Format
    1113
  - Figure 26.3 Master Data Transmit Format
    1113
  - Figure 26.4 Master Data Receive Format
    1113
  - 10-Bit Address Format
    1114
  - Figure 26.5 Combination Transfer Format of Master Transfer
    1114
  - Figure 26.6 10-Bit Address Data Transmit Format
    1114
  - Figure 26.7 10-Bit Address Data Receive Format
    1115
  - Figure 26.8 10-Bit Address Transmit/Receive Combined Format
    1115
  - Master Transmit Operation
    1116
  - Figure 26.9 Data Transmit Mode Operation Timing
    1117
  - Master Receive Operation
    1118
  - Figure 26.10 Data Receive Mode Operation Timing
    1119
- Programming Examples
  1120
  - Master Transmitter
    1120
  - Master Receiver
    1121
  - Master Transmitter-Restart-Master Receiver
    1122
Section 27 Serial Communication Interface with FIFO (SCIF)

1125
Section 28 Serial Communication Interface with Fifo/Irda Interface (Scif/Irda)

1185
Section 29 Serial I/O with FIFO (SIOF)

1251
- Features
  1251
- Figure 29.1 Block Diagram of SIOF
  1252
- Input/Output Pins
  1253
- Table 29.1 Pin Configuration
  1253
- Register Descriptions
  1254
  - Table 29.2 Register Configuration
    1254
  - Table 29.3 Register State in each Operating Mode
    1256
  - Mode Register (SIMDR)
    1258
  - Clock Select Register (SISCR)
    1260
  - Table 29.4 Operation in each Transfer Mode
    1260
  - Control Register (SICTR)
    1262
  - Transmit Data Register (SITDR)
    1265
  - Receive Data Register (SIRDR)
    1266
  - Transmit Control Data Register (SITCR)
    1267
  - Receive Control Data Register (SIRCR)
    1268
  - Status Register (SISTR)
    1269
  - Interrupt Enable Register (SIIER)
    1275
  - FIFO Control Register (SIFCTR)
    1277
  - Transmit Data Assign Register (SITDAR)
    1279
  - Receive Data Assign Register (SIRDAR)
    1280
  - Control Data Assign Register (SICDAR)
    1281
- Operation
  1283
Section 30 SIM Card Module (SIM)

1307
- Features
  1307
- Figure 30.1 Smart Card Interface
  1308
- Input/Output Pins
  1309
- Table 30.1 Pin Configuration
  1309
- Register Descriptions
  1310
  - Table 30.2 Register Configuration
    1310
  - Table 30.3 Register State in each Operating Mode
    1311
  - Serial Mode Register (SCSMR)
    1312
  - Bit Rate Register (SCBRR)
    1313
  - Serial Control Register (SCSCR)
    1314
  - Transmit Shift Register (SCTSR)
    1316
  - Transmit Data Register (SCTDR)
    1317
  - Serial Status Register (SCSSR)
    1318
  - Receive Data Register (SCRDR)
    1324
  - Receive Shift Register (SCRSR)
    1324
  - Smart Card Mode Register (SCSCMR)
    1325
  - Serial Control 2 Register (SCSC2R)
    1327
  - Guard Extension Register (SCGRD)
    1328
  - Wait Time Register (SCWAIT)
    1329
  - Sampling Register (SCSMPL)
    1330
- Operation
  1331
  - Overview
    1331
  - Data Format
    1332
  - Figure 30.2 Data Format Used by Smart Card Interface
    1332
  - Register Settings
    1333
  - Table 30.4 Register Settings for Smart Card Interface
    1334
  - Clocks
    1335
  - Figure 30.3 Examples of Start Character Waveforms
    1335
  - Data Transmit/Receive Operation
    1336
  - Table 30.5 Example of Bit Rates (Bits/S) for SCBRR Settings (Pck0 = 66.6 Mhz, SCSMPL = 371)
    1336
  - Figure 30.4 Example of Initialization Flow
    1337
  - Figure 30.5 Example of Transmit Processing
    1339
  - Figure 30.6 Example of Receive Processing
    1341
  - Table 30.6 Interrupt Sources of Smart Card Interface
    1342
- Usage Notes
  1344
- Figure 30.7 Receive Data Sampling Timing in Smart Card Mode
  1344
- Figure 30.8 Retransmission When Smart Card Interface Is in Receive Mode
  1345
- Figure 30.9 Retransmit Standby Mode (Clock Stopped) When Smart Card Interface Is in Transmit Mode
  1346
- Figure 30.10 Procedure for Stopping Clock and Restarting
  1347
- Figure 30.11 Example of Pin Connections in Smart Card Interface
  1348
- Figure 30.12 TEIE Set Timing
  1349
Section 31 Multimedia Card Interface (MMCIF)

1351
Section 32 PC Card Controller (PCC)

1425
- Features
  1425
- Input/Output Pins
  1430
- Table 32.2 PCC Pin Configuration
  1430
- Register Descriptions
  1431
- Operation
  1446
- Usage Notes
  1455
Section 33 Audio Codec Interface (HAC)

1457
- Features
  1457
- Input/Output Pins
  1458
- Figure 33.1 Block Diagram
  1458
- Table 33.1 Pin Configuration
  1458
- Register Descriptions
  1459
  - Table 33.2 Register Configuration
    1459
  - Table 33.3 Register State in each Operating Mode
    1459
  - Control and Status Register (HACCR)
    1460
  - Command/Status Address Register (HACCSAR)
    1462
  - Command/Status Data Register (HACCSDR)
    1464
  - PCM Left Channel Register (HACPCML)
    1465
  - PCM Right Channel Register (HACPCMR)
    1467
  - TX Interrupt Enable Register (HACTIER)
    1468
  - TX Status Register (HACTSR)
    1469
  - RX Interrupt Enable Register (HACRIER)
    1471
  - RX Status Register (HACRSR)
    1472
  - HAC Control Register (HACACR)
    1473
- AC 97 Frame Slot Structure
  1475
- Figure 33.2 AC97 Frame Slot Structure
  1475
- Table 33.4 AC97 Transmit Frame Structure
  1475
- Operation
  1476
  - Receiver
    1476
  - Table 33.5 AC97 Receive Frame Structure
    1476
  - Transmitter
    1477
  - Dma
    1477
  - Interrupts
    1477
  - Initialization Sequence
    1478
  - Figure 33.3 Initialization Sequence
    1478
  - Figure 33.4 Sample Flowchart for Off-Chip Codec Register Write
    1479
  - Figure 33.5 Sample Flowchart for Off-Chip Codec Register Read (1)
    1480
  - Figure 33.6 Sample Flowchart for Off-Chip Codec Register Read (2)
    1481
  - Figure 33.7 Sample Flowchart for Off-Chip Codec Register Read (3)
    1482
  - Notes
    1483
  - Reference
    1483
Section 34 Serial Sound Interface (SSI)

1485
Section 35 USB Host Controller (USBH)

1523
- Features
  1523
- Figure 35.1 Block Diagram of USBH
  1524
- Pin Description
  1525
- Table 35.1 USB Host Pin Assignment
  1525
- Register Description
  1526
  - Table 35.2 Register Configuration
    1526
  - Table 35.3 Register State in each Operating Mode
    1527
  - Hcrevision Register (USBHR)
    1528
  - Hccontrol Register (USBHC)
    1529
  - Hccommandstatus Register (USBHCS)
    1531
  - Hcinterruptstatus Register (USBHIS)
    1532
  - Hcinterruptenable Register (USBHIE)
    1534
  - Hcinterruptdisable Register (USBHID)
    1535
  - Hchcca Register (USBHHCCA)
    1537
  - Hcperiodcurrented Register (USBHPCED)
    1537
  - Hccontrolcurrented Register (USBHCCED)
    1538
  - Hccontrolheaded Register (USBHCHED)
    1538
  - Hcbulkcurrented Register (USBHBCED)
    1539
  - Hcbulkheaded Register (USBHBHED)
    1539
  - Hcdonehead Register (USBHDHED)
    1540
  - Hcfminterval Register (USBHFI)
    1541
  - Hcframeremaining Register (USBHFR)
    1542
  - Hcfmnumber Register (USBHFN)
    1543
  - Hcperiodicstart Register (USBHPS)
    1544
  - Hclsthreshold Register (USBHLST) (Not Supporting Lowspeed Mode)
    1545
  - Hcrhdescriptora Register (USBHRDA) (Only One Port Is Supported by this LSI.)
    1546
  - Hcrhdescriptorb Register (USBHRDB) (Only One Port Is Supported by this LSI.)
    1548
  - Hcrhstatus Register (USBHRS)
    1550
  - Hcrhportstatus[2] Register (USBHRPS2)
    1552
  - Configurationcontrol Register (USBHSC)
    1555
- Functional Description
  1557
  - General Functionality
    1557
- Connection Example of an External Circuit
  1559
- Usage Notes
  1559
  - External Memory that USBH Accesses
    1559
  - Issuing USB Bus Reset
    1559
  - Figure 35.2 Connection Example of External Circuit
    1559
Section 36 USB Function Controller (USBF)

1561
- Features
  1561
- Figure 36.1 Block Diagram of USBF
  1562
- Input/Output Pins
  1563
- Table 36.1 Pin Configuration and Functions
  1563
- Register Descriptions
  1564
  - Table 36.3 Register State in each Operating Mode
    1568
  - Interrupt Flag Register 0 (IFR0)
    1570
  - Interrupt Flag Register 1 (IFR1)
    1573
  - Interrupt Flag Register 2 (IFR2)
    1575
  - Interrupt Flag Register 3 (IFR3)
    1577
  - Interrupt Flag Register 4 (IFR4)
    1580
  - Interrupt Select Register 0 (ISR0)
    1581
  - Interrupt Select Register 1 (ISR1)
    1582
  - Interrupt Select Register 2 (ISR2)
    1583
  - Interrupt Select Register 3 (ISR3)
    1584
  - Interrupt Select Register 4 (ISR4)
    1585
  - Interrupt Enable Register 0 (IER0)
    1586
  - Interrupt Enable Register 1 (IER1)
    1587
  - Interrupt Enable Register 2 (IER2)
    1588
  - Interrupt Enable Register 3 (IER3)
    1589
  - Interrupt Enable Register 4 (IER4)
    1590
  - Ep0I Data Register (Epdr0I)
    1591
  - Ep0O Data Register (Epdr0O)
    1592
  - Ep0S Data Register (Epdr0S)
    1593
  - EP1 Data Register (EPDR1)
    1594
  - EP2 Data Register (EPDR2)
    1595
  - EP3 Data Register (EPDR3)
    1596
  - EP4 Data Register (EPDR4)
    1597
  - EP5 Data Register (EPDR5)
    1598
  - Ep0O Receive Data Size Register (Epsz0O)
    1599
  - EP1 Receive Data Size Register (EPSZ1)
    1600
  - EP4 Receive Data Size Register (EPSZ4)
    1601
  - Trigger Register (TRG)
    1602
  - Data Status Register (DASTS)
    1603
  - FIFO Clear Register 0 (FCLR0)
    1604
  - FIFO Clear Register 1 (FCLR1)
    1605
  - DMA Transfer Setting Register (DMA)
    1606
  - Endpoint Stall Register 0 (EPSTL0)
    1607
  - Endpoint Stall Register 1 (EPSTL1)
    1608
  - Configuration Value Register (CVR)
    1609
  - Time Stamp Register (TSRH/TSRL)
    1610
  - Control Register 0 (CTLR0)
    1612
  - Control Register 1 (CTLR1)
    1614
  - Endpoint Information Register (EPIR)
    1615
  - Table 36.4 Restrictions of Settable Values
    1619
  - Table 36.5 Example of Endpoint Configuration
    1619
  - Figure 36.2 Example of Endpoint Configuration
    1620
  - Table 36.6 Example of Setting of Endpoint Configuration Information
    1620
  - Timer Register (TMRH/TMRL)
    1621
  - Set Time out Register (STOH/STOL)
    1623
- Operation
  1625
  - Cable Connection
    1625
  - Figure 36.3 Cable Connection Operation
    1625
  - Cable Disconnection
    1626
  - Figure 36.4 Cable Disconnection Operation
    1626
  - Figure 36.5 Setup Stage Operation
    1627
  - Figure 36.6 Data Stage (Control-In) Operation
    1628
  - Figure 36.7 Data Stage (Control-Out) Operation
    1629
  - Figure 36.8 Status Stage (Control-In) Operation
    1630
  - Figure 36.9 Status Stage (Control-Out) Operation
    1631
  - EP1 Bulk-Out Transfer (Dual Fifos)
    1632
  - Figure 36.10 EP1 Bulk-Out Transfer Operation
    1632
  - EP2 Bulk-In Transfer (Dual Fifos)
    1633
  - Figure 36.11 EP2 Bulk-In Transfer Operation
    1633
  - EP3 Interrupt-In Transfer
    1635
  - Figure 36.12 EP3 Interrupt-In Transfer Operation
    1635
- EP4 Isochronous-Out Transfer
  1636
- Figure 36.13 EP4 Isochronous-Out Transfer Operation (SOF Is Normal)
  1636
- Figure 36.14 EP4 Isochronous-Out Transfer Operation (SOF Is Broken)
  1637
- EP5 Isochronous-In Transfer
  1639
- Figure 36.15 EP5 Isochronous-In Transfer Operation (SOF Is Normal)
  1639
- Figure 36.16 EP5 Isochronous-In Transfer Operation (SOF in Broken)
  1640
- Processing of USB Standard Commands and Class/Vendor Commands
  1642
  - Processing of Commands Transmitted by Control Transfer
    1642
  - Table 36.7 Command Decoding on Application Side
    1642
- Stall Operations
  1643
  - Overview
    1643
  - Forcible Stall by Application
    1643
  - Figure 36.17 Forcible Stall by Application
    1644
  - Automatic Stall by USB Function Controller
    1645
  - Figure 36.18 Automatic Stall by USB Function Controller
    1646
- Examples of External Circuit
  1647
  - Example of the Connection between USB Function Controller
    1647
  - Figure 36.19 Example of Transceiver Connection for USB Function Controller
    1647
- Usage Notes
  1648
  - 36.10.1 Setup Data Reception
    1648
  - 36.10.2 FIFO Clear
    1648
  - 36.10.3 Overreading/Overwriting of Data Register
    1648
  - 36.10.4 Assigning EP0 Interrupt Sources
    1649
  - 36.10.5 FIFO Clear When DMA Transfer Is Set
    1649
  - 36.10.6 Note on Using TR Interrupt
    1649
  - Figure 36.20 Set Timing of TR Interrupt Flag
    1650
Section 37 LCD Controller (LCDC)

1651
Section 38 A/D Converter

1721
- Features
  1721
- Figure 38.1 Block Diagram of A/D Converter
  1722
- Input Pins
  1723
- Table 38.1 Pin Configuration
  1723
- Register Descriptions
  1724
- Operation
  1729
- Interrupts
  1734
- Table 38.5 A/D Conversion Time
  1734
- Definitions of A/D Conversion Accuracy
  1735
- Figure 38.5 Definitions of A/D Conversion Accuracy
  1736
- Usage Notes
  1737
  - Setting Analog Input Voltage
    1737
  - Processing of Analog Input Pins
    1737
  - Figure 38.6 Example of Analog Input Pin Protection Circuit
    1737
  - Pck0 Clock and Clock Division Ratio Settings
    1738
  - A/D Conversion Stop
    1738
Section 39 D/A Converter (DAC)

1739
- Features
  1739
- Figure 39.1 Block Diagram of D/A Converter
  1739
- Input/Output Pins
  1740
- Register Descriptions
  1740
  - Table 39.1 Pin Configuration
    1740
  - Table 39.2 Register Configuration
    1740
  - Table 39.3 Register State in each Operating Mode
    1740
  - D/A Data Registers 0 and 1 (DADR0, DADR1)
    1741
  - D/A Control Register (DACR)
    1742
- Operation
  1743
- Figure 39.2 D/A Converter Operation Example
  1743
- Usage Notes
  1744
Section 40 General Purpose I/O (GPIO)

1745
- Features
  1745
- Table 40.1 Multiplexed Pins Controlled by Port Control Registers
  1746
- Register Descriptions
  1756
  - Table 40.2 Register Configuration (1)
    1756
  - Table 40.3 Register States in each Operating Mode
    1758
  - Port a Control Register (PACR)
    1759
  - Port B Control Register (PBCR)
    1761
  - Port C Control Register (PCCR)
    1762
  - Port D Control Register (PDCR)
    1764
  - Port E Control Register (PECR)
    1766
  - Port F Control Register (PFCR)
    1767
  - Port G Control Register
    1769
  - Port H Control Register (PHCR)
    1771
  - Port I Control Register (PICR)
    1773
  - Port J Control Register (PJCR)
    1775
  - Port K Control Register (PKCR)
    1777
  - Port L Control Register (PLCR)
    1779
  - Port M Control Register (PMCR)
    1781
  - Port N Control Register (PNCR)
    1783
  - Port O Control Register (POCR)
    1785
  - Port a Data Register (PADR)
    1787
  - Port B Data Register (PBDR)
    1788
  - Port C Data Register (PCDR)
    1789
  - Port D Data Register (PDDR)
    1790
  - Port E Data Register (PEDR)
    1791
  - Port F Data Register (PFDR)
    1792
  - Port G Data Register
    1793
  - Port H Data Register (PHDR)
    1794
  - Port I Data Register (PIDR)
    1795
  - Port J Data Register (PJDR)
    1796
  - Port K Data Register (PKDR)
    1797
  - Port L Data Register (PLDR)
    1798
  - Port M Data Register (PMDR)
    1799
  - Port N Data Register (PNDR)
    1800
  - Port O Data Register (PODR)
    1801
  - Port I Pull-Up Control Register (PIPUPR)
    1802
  - Port J Pull-Up Control Register (PJPUPR)
    1803
  - Port K Pull-Up Control Register (PKPUPR)
    1804
  - Port L Pull-Up Control Register (PLPUPR)
    1805
  - Port M Pull-Up Control Register (PMPUPR)
    1806
  - Port N Pull-Up Control Register (PNPUPR)
    1808
  - Port O Pull-Up Control Register (POPUPR)
    1809
  - Input-Pin Pull-Up Control Register (PPUPR)
    1810
  - Pin Select Register 0 (PSEL0)
    1811
  - Pin Select Register 1 (PSEL1)
    1812
  - Pin Select Register 2 (PSEL2)
    1815
  - Pin Select Register 3 (PSEL3)
    1818
  - Pin Select Register 4 (PSEL4)
    1821
- Usage Examples
  1824
  - Port Output Function
    1824
  - Port Input Function
    1824
  - Peripheral Module Function
    1824
Section 41 User Break Controller (UBC)

1825
- Features
  1825
- Figure 41.1 Block Diagram of UBC
  1826
- Register Descriptions
  1827
- Operation Description
  1847
  - Definition of Words Related to Accesses
    1847
  - User Break Operation Sequence
    1848
  - Instruction Fetch Cycle Break
    1850
  - Operand Access Cycle Break
    1851
  - Table 41.4 Relation between Operand Sizes and Address Bits to be Compared
    1851
  - Sequential Break
    1853
  - Program Counter Value to be Saved
    1854
- User Break Debugging Support Function
  1855
- Figure 41.2 Flowchart of User Break Debugging Support Function
  1856
- User Break Examples
  1857
- Usage Notes
  1861
Section 42 User Debugging Interface (H-UDI)

1863
- Features
  1863
- Figure 42.1 H-UDI Block Diagram
  1864
- Input/Output Pins
  1865
- Table 42.1 Pin Configuration
  1865
- Boundary Scan TAP Controllers (IDCODE, EXTEST, SAMPLE/PRELOAD, and BYPASS)
  1866
- Figure 42.2 Sequence for Switching from Boundary-Scan TAP Controller to H-UDI
  1867
- Table 42.2 Commands Supported by Boundary-Scan TAP Controller
  1867
- Register Descriptions
  1868
  - Table 42.3 Register Configuration (1)
    1868
  - Table 42.4 Register Configuration (2)
    1868
  - Table 42.5 Register Status in each Processing State
    1868
  - Instruction Register (SDIR)
    1869
  - Interrupt Source Register (SDINT)
    1870
  - Boundary Scan Register (SDBSR)
    1871
  - Bypass Register (SDBPR)
    1871
  - Table 42.6 SDBSR Configuration
    1872
- Operation
  1889
  - TAP Control
    1889
  - Figure 42.3 TAP Controller State Transitions
    1889
  - H-UDI Reset
    1890
  - H-UDI Interrupt
    1890
- Usage Notes
  1890
- Figure 42.4 H-UDI Reset
  1890
Section 43 Electrical Characteristics

1891
Appendix

1969
- CPU Operation Mode Register (CPUOPM)
  1969
- Instruction Prefetching and Its Side Effects
  1971
- Figure B.1 Instruction Prefetch
  1971
- Speculative Execution for Subroutine Return
  1972
- List of Mode Control Pins and Schematic Diagram of External Cicuits
  1973
- Table D.1 Mode Control Pins
  1973
- Figure D.1 Schematic Diagram of External Circuits
  1974
- Notes on Board Design
  1975
- Figure E.1 Connection Example of Bypass Capacitors for Analog Power Supply
  1977
- Package Dimensions
  1978
- Figure F.1 Package Dimensions (449-Pin)
  1978
- Pin States
  1979
- Table G.1 Pin States
  1979
- Handling of Unused Pins
  1997
- Table H.1 Handling of Unused Pins
  1997
- Version Registers
  2009
- Table I.1 Register Configuration
  2009
- Heat Radiation
  2010
- Table J.1 Heat Resistance Simulation Results
  2011
- Figure J.2 Heat Sink Model
  2012
Index

2013

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Renesas SH7763 Hardware Manual (2026 pages)

Table of Contents

Section 2 Programming Model

Section 3 Instruction Set

Section 4 Pipelining

Section 5 Exception Handling

Section 6 Memory Management Unit (MMU)

Section 7 Caches

Section 8 L Memory

Section 9 Interrupt Controller (INTC)

Section 10 Superhyway Bus Bridge (SBR)

Section 11 Local Bus State Controller (LBSC)

Section 12 DDR-SDRAM Interface (DDRIF)

Section 13 PCI Controller (PCIC)

Section 14 Direct Memory Access Controller (DMAC)

Section 15 External CPU Interface (EXCPU)

Section 16 Clock Pulse Generator (CPG)

Section 17 Watchdog Timer and Reset (WDT)

Section 18 Power-Down Mode

Section 19 Timer Unit (TMU)

Section 20 16-Bit Timer Pulse Unit (TPU)

Section 21 Compare Match Timer (CMT)

Section 22 Realtime Clock (RTC)

Section 23 Gigabit Ethernet Controller (GETHER)

Section 24 IP Security Accelerator (SECURITY)

Section 25 Stream Interface (STIF)

Section 26 I C Bus Interface (IIC)

Section 27 Serial Communication Interface with FIFO (SCIF)

Section 28 Serial Communication Interface with Fifo/Irda Interface (Scif/Irda)

Section 29 Serial I/O with FIFO (SIOF)

Section 30 SIM Card Module (SIM)

Section 31 Multimedia Card Interface (MMCIF)

Section 32 PC Card Controller (PCC)

Section 33 Audio Codec Interface (HAC)

Section 34 Serial Sound Interface (SSI)

Section 35 USB Host Controller (USBH)

Section 36 USB Function Controller (USBF)

Section 37 LCD Controller (LCDC)

Section 38 A/D Converter

Section 39 D/A Converter (DAC)

Section 40 General Purpose I/O (GPIO)

Section 41 User Break Controller (UBC)

Section 42 User Debugging Interface (H-UDI)

Section 43 Electrical Characteristics

Appendix

Index

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